公开(公告)号：US20220196914A1

公开(公告)日：2022-06-23

申请号：US17131678

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Jeremy D. ECTON ,  Hiroki TANAKA ,  Brandon C. MARIN ,  Srinivas V. PIETAMBARAM ,  Gang DUAN ,  Bai NIE ,  Haobo CHEN ,  Zhichao ZHANG ,  Sai VADLAMANI ,  Aleksandar ALEKSOV

IPC: G02B6/12 ,  H01L23/48 ,  G02B6/02 ,  H01L25/065

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such structures. In an embodiment, an electronic package comprises a package substrate, a first die over the package substrate, and a second die over the package substrate. In an embodiment, the electronic package further comprises an optical waveguide on the package substrate. In an embodiment, a first end of the optical waveguide is below the first die and a second end of the optical waveguide is below the second die. In an embodiment, the optical waveguide communicatively couples the first die to the second die.

公开(公告)号：US20220187549A1

公开(公告)日：2022-06-16

申请号：US17122352

申请日：2020-12-15

Applicant: Intel Corporation

Inventor： Hiroki TANAKA ,  Brandon C. MARIN ,  Kristof DARMAWKARTA ,  Robert Alan MAY ,  Sri Ranga Sai BOYAPATI ,  Srinivas V. PIETAMBARAM

IPC: G02B6/42

Abstract: Embodiments disclosed herein include photonics package with Faraday rotators to improve efficiency. In an embodiment, a photonics package comprises a package substrate and a compute die over the package substrate. In an embodiment, the photonics package further comprises a photonics die over the package substrate. In an embodiment, the compute die is communicatively coupled to the photonics die by a bridge in the package substrate. In an embodiment, the photonics package further comprises an integrated heat spreader (IHS) over the package substrate, and a Faraday rotator passing through the IHS and optically coupled to the photonics die.

公开(公告)号：US20220165695A1

公开(公告)日：2022-05-26

申请号：US17104919

申请日：2020-11-25

Applicant: Intel Corporation

Inventor： Numair AHMED ,  Kyu-Oh LEE ,  Brandon C. MARIN ,  Gang DUAN

IPC: H01L23/00 ,  H01L23/498

Abstract: Embodiments disclosed herein include electronic packages with fin pitch first level interconnects. In an embodiment, the electronic package comprises a die and a package substrate attached to the die by a plurality of first level interconnects (FLIs). In an embodiment, individual ones of the plurality of FLIs comprise, a first pad on the package substrate, a solder on the first pad, a second pad on the die, and a bump on the second pad. In an embodiment, the bump comprises a porous nanostructure, and the solder at least partially fills the porous nanostructure.

公开(公告)号：US20210028101A1

公开(公告)日：2021-01-28

申请号：US16522483

申请日：2019-07-25

Applicant: Intel Corporation

Inventor： Bai NIE ,  Haobo CHEN ,  Gang DUAN ,  Brandon C. MARIN ,  Srinivas PIETAMBARAM

IPC: H01L23/498 ,  H01L23/66 ,  H01L21/48

Abstract: Embodiments disclosed herein include electronic packages and methods of making such packages. In an embodiment, a package substrate comprises a substrate comprising a first dielectric material, a first trace embedded in the substrate, and a patch in direct contact with the first trace. In an embodiment, the patch comprises a second dielectric material that is different than the first dielectric material.

公开(公告)号：US20200373261A1

公开(公告)日：2020-11-26

申请号：US16421989

申请日：2019-05-24

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Jeremy D. ECTON ,  Aleksandar ALEKSOV ,  Kristof DARMAWIKARTA ,  Yonggang LI ,  Dilan SENEVIRATNE

IPC: H01L23/66 ,  H01P7/10 ,  H01P3/16 ,  H01L21/768 ,  H01P11/00 ,  H01L21/288

Abstract: A filter structure comprises a first dielectric buildup film. A second dielectric buildup film is over the first dielectric buildup film, the second dielectric buildup film including a metallization catalyst. A trench is in the second dielectric buildup film. A metal is selectively plated to sidewalls of the trench based at least in part on the metallization catalyst. A low-loss buildup film is over the metal that substantially fills the trench.

公开(公告)号：US20200373157A1

公开(公告)日：2020-11-26

申请号：US16419426

申请日：2019-05-22

Applicant: Intel Corporation

Inventor： Jeremy D. ECTON ,  Brandon C. MARIN ,  Andrew J. BROWN ,  Dilan SENEVIRATNE

IPC: H01L21/02 ,  H01L49/02 ,  H01L23/532 ,  H01L21/768

Abstract: A thin-film insulator comprises a first electrode over a substrate. A photo up-converting material is over the first electrode. A cured photo-imageable dielectric (PID) containing a high-k filler material is over the photo up-converting material, wherein the cured PID is less than 4 μm in thickness, and a second electrode is over the cured PID.

公开(公告)号：US20200328131A1

公开(公告)日：2020-10-15

申请号：US16380486

申请日：2019-04-10

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Kristof DARMAWIKARTA ,  Roy DITTLER ,  Jeremy ECTON ,  Darko GRUJICIC

IPC: H01L23/31 ,  H01L23/488

Abstract: Embodiments disclosed herein include electronic packages with a ground plate embedded in the solder resist that extends over signal traces. In an embodiment, the electronic package comprises a substrate layer, a trace over the substrate layer, and a first pad over the substrate layer. In an embodiment, a solder resist is disposed over the trace and the first pad. In an embodiment a trench is formed into the solder resist, and the trench extends over the trace. In an embodiment, a conductive plate is disposed in the trench, and is electrically coupled to the first pad by a via that extends from a bottom surface of the trench through the solder resist.

公开(公告)号：US20200258800A1

公开(公告)日：2020-08-13

申请号：US16274091

申请日：2019-02-12

Applicant: Intel Corporation

Inventor： Jeremy ECTON ,  Oscar OJEDA ,  Leonel ARANA ,  Suddhasattwa NAD ,  Robert MAY ,  Hiroki TANAKA ,  Brandon C. MARIN

IPC: H01L23/31 ,  H05K1/02 ,  H05K3/06 ,  H01L21/283

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a substrate and a conductive feature over the substrate. In an embodiment, a metallic mask is positioned over the conductive feature. In an embodiment, the metallic mask extends beyond a first edge of the conductive feature and a second edge of the conductive feature.

公开(公告)号：US20160374210A1

公开(公告)日：2016-12-22

申请号：US14905022

申请日：2015-02-16

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Trina GHOSH DASTIDAR ,  Yonggang Yong LI ,  Dilan SENEVIRATNE

IPC: H05K3/18 ,  H01L21/288 ,  H05K1/03 ,  H01L23/528 ,  H01L23/532 ,  H05K1/09 ,  H01L21/768 ,  H05K3/00

CPC classification number: H05K3/187 ,  H01L21/288 ,  H01L21/4857 ,  H01L21/76802 ,  H01L21/76829 ,  H01L21/76874 ,  H01L21/76877 ,  H01L23/49894 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/5329 ,  H05K1/036 ,  H05K1/09 ,  H05K3/0032 ,  H05K3/105 ,  H05K3/182 ,  H05K2201/09036

Abstract: A build-up layer may be fabricated by forming a microelectronic dielectric layer comprising a dielectric material with a metallization catalyst dispersed therein, forming a primer layer on the microelectronic dielectric layer, and forming a recess through the primer layer and into the dielectric material layer. An activation layer may be formed in or on the exposed microelectronic dielectric layer within the recess, wherein the primer layer acts as a mask. A metal layer may be formed on the activation layer, such as with an electroless process. Thus, the resolution of the metal layer deposition may be precisely controlled by the process used to form the recess.

Abstract translation: 可以通过形成包含分散在其中的金属化催化剂的电介质材料的微电子介电层来形成堆积层，在微电子介电层上形成底漆层，以及通过底涂层形成凹陷并进入电介质材料层。 活化层可以形成在凹陷内的暴露的微电子介电层中或其上，其中底漆层用作掩模。 可以在活化层上形成金属层，例如用无电解方法。 因此，可以通过用于形成凹部的工艺来精确地控制金属层沉积的分辨率。