公开(公告)号：US20250112136A1

公开(公告)日：2025-04-03

申请号：US18374937

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Bohan SHAN ,  Jesse JONES ,  Zhixin XIE ,  Bai NIE ,  Shaojiang CHEN ,  Joshua STACEY ,  Mitchell PAGE ,  Brandon C. MARIN ,  Jeremy D. ECTON ,  Nicholas S. HAEHN ,  Astitva TRIPATHI ,  Yuqin LI ,  Edvin CETEGEN ,  Jason M. GAMBA ,  Jacob VEHONSKY ,  Jianyong MO ,  Makoyi WATSON ,  Shripad GOKHALE ,  Mine KAYA ,  Kartik SRINIVASAN ,  Haobo CHEN ,  Ziyin LIN ,  Kyle ARRINGTON ,  Jose WAIMIN ,  Ryan CARRAZZONE ,  Hongxia FENG ,  Srinivas Venkata Ramanuja PIETAMBARAM ,  Gang DUAN ,  Dingying David XU ,  Hiroki TANAKA ,  Ashay DANI ,  Praveen SREERAMAGIRI ,  Yi LI ,  Ibrahim EL KHATIB ,  Aaron GARELICK ,  Robin MCREE ,  Hassan AJAMI ,  Yekan WANG ,  Andrew JIMENEZ ,  Jung Kyu HAN ,  Hanyu SONG ,  Yonggang Yong LI ,  Mahdi MOHAMMADIGHALENI ,  Whitney BRYKS ,  Shuqi LAI ,  Jieying KONG ,  Thomas HEATON ,  Dilan SENEVIRATNE ,  Yiqun BAI ,  Bin MU ,  Mohit GUPTA ,  Xiaoying GUO

IPC: H01L23/498 ,  H01L23/15

Abstract: Embodiments disclosed herein include apparatuses with glass core package substrates. In an embodiment, an apparatus comprises a substrate with a first surface and a second surface opposite from the first surface. A sidewall is between the first surface and the second surface, and the substrate comprises a glass layer. In an embodiment, a via is provided through the substrate between the first surface and the second surface, and the via is electrically conductive. In an embodiment, a layer in contact with the sidewall of the substrate surrounds a perimeter of the substrate.

公开(公告)号：US20160374210A1

公开(公告)日：2016-12-22

申请号：US14905022

申请日：2015-02-16

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Trina GHOSH DASTIDAR ,  Yonggang Yong LI ,  Dilan SENEVIRATNE

IPC: H05K3/18 ,  H01L21/288 ,  H05K1/03 ,  H01L23/528 ,  H01L23/532 ,  H05K1/09 ,  H01L21/768 ,  H05K3/00

CPC classification number: H05K3/187 ,  H01L21/288 ,  H01L21/4857 ,  H01L21/76802 ,  H01L21/76829 ,  H01L21/76874 ,  H01L21/76877 ,  H01L23/49894 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/5329 ,  H05K1/036 ,  H05K1/09 ,  H05K3/0032 ,  H05K3/105 ,  H05K3/182 ,  H05K2201/09036

Abstract: A build-up layer may be fabricated by forming a microelectronic dielectric layer comprising a dielectric material with a metallization catalyst dispersed therein, forming a primer layer on the microelectronic dielectric layer, and forming a recess through the primer layer and into the dielectric material layer. An activation layer may be formed in or on the exposed microelectronic dielectric layer within the recess, wherein the primer layer acts as a mask. A metal layer may be formed on the activation layer, such as with an electroless process. Thus, the resolution of the metal layer deposition may be precisely controlled by the process used to form the recess.

Abstract translation: 可以通过形成包含分散在其中的金属化催化剂的电介质材料的微电子介电层来形成堆积层，在微电子介电层上形成底漆层，以及通过底涂层形成凹陷并进入电介质材料层。 活化层可以形成在凹陷内的暴露的微电子介电层中或其上，其中底漆层用作掩模。 可以在活化层上形成金属层，例如用无电解方法。 因此，可以通过用于形成凹部的工艺来精确地控制金属层沉积的分辨率。

公开(公告)号：US20250112140A1

公开(公告)日：2025-04-03

申请号：US18374609

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Rahul BHURE ,  Mitchell PAGE ,  Joseph PEOPLES ,  Jieying KONG ,  Nicholas S. HAEHN ,  Astitva TRIPATHI ,  Bainye Francoise ANGOUA ,  Yosef KORNBLUTH ,  Daniel ROSALES-YEOMANS ,  Joshua STACEY ,  Aaditya Anand CANDADAI ,  Yonggang Yong LI ,  Tchefor NDUKUM ,  Scott COATNEY ,  Gang DUAN ,  Jesse JONES ,  Srinivas Venkata Ramanuja PIETAMBARAM ,  Dilan SENEVIRATNE ,  Matthew ANDERSON

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/15

Abstract: Embodiments disclosed herein include package substrates with a glass core. In an embodiment, an apparatus comprises a core with a first width, and the core comprises a glass layer. In an embodiment, a via is provided through a thickness of the core, where the via is electrically conductive. In an embodiment, a first layer is provided over the core, where the first layer comprises a second width that is smaller than the first width. In an embodiment, a second layer is provided under the core, where the second layer comprises a third width that is smaller than the first width.

公开(公告)号：US20250113434A1

公开(公告)日：2025-04-03

申请号：US18374617

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Bai NIE ,  Mitchell PAGE ,  Junxin WANG ,  Srinivas Venkata Ramanuja PIETAMBARAM ,  Haifa HARIRI ,  Nicholas S. HAEHN ,  Astitva TRIPATHI ,  Yuqin LI ,  Hongxia FENG ,  Haobo CHEN ,  Bohan SHAN ,  Hiroki TANAKA ,  Leonel R. ARANA ,  Yonggang Yong LI

IPC: H05K1/02 ,  H01L23/15 ,  H01L23/498 ,  H05K1/03 ,  H05K1/11

Abstract: Embodiments disclosed herein include package substrates with a glass core. In an embodiment, an apparatus comprises a substrate with a first surface and a second surface opposite from the first surface, and the substrate is a solid glass layer. In an embodiment, an opening is provided through a thickness of the substrate, where the opening comprises a sidewall that is non-orthogonal with the first surface of the substrate. In an embodiment a corner at a junction between the sidewall and the first surface is rounded. In an embodiment, a via is provided in the opening, where the via is electrically conductive.

公开(公告)号：US20170243762A1

公开(公告)日：2017-08-24

申请号：US15588500

申请日：2017-05-05

Applicant: Intel Corporation

Inventor： Yonggang Yong LI ,  Aritra DHAR ,  Dilan SENEVIRATNE ,  Jon M. WILLIAMS

IPC: H01L21/48 ,  C23C18/38 ,  C23C18/16 ,  H01L21/288 ,  H01L23/498

CPC classification number: H01L21/4857 ,  C23C18/1608 ,  C23C18/1612 ,  C23C18/2086 ,  C23C18/30 ,  C23C18/38 ,  H01L21/288 ,  H01L21/486 ,  H01L21/4864 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49866 ,  H01L24/17 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K3/0032 ,  H05K3/045 ,  H05K3/107 ,  H05K3/185 ,  H05K2201/0236 ,  H05K2203/072 ,  H05K2203/107

Abstract: Embodiments describe the selective electroless plating of dielectric layers. According to an embodiment, a dielectric layer is patterned to form one or more patterned surfaces. A seed layer is then selectively formed along the patterned surfaces of the dielectric layer. An electroless plating process is used to deposit metal only on the patterned surfaces of the dielectric layer. According to an embodiment, the dielectric layer is doped with an activator precursor. Laser assisted local activation is performed on the patterned surfaces of the dielectric layer in order to selectively form a seed layer only on the patterned surfaces of the dielectric layer by reducing the activator precursor to an oxidation state of zero. According to an additional embodiment, a seed layer is selectively formed on the patterned surfaces of the dielectric layer with a colloidal or ionic seeding solution.