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    Apparatus and method to track device usage
    51.
    发明授权
    Apparatus and method to track device usage 有权
    跟踪设备使用的装置和方法

    公开(公告)号：US09535812B2

    公开(公告)日：2017-01-03

    申请号：US13930212

    申请日：2013-06-28

    Applicant: Intel Corporation

    Inventor： Doron Rajwan ,  Nadav Shulman ,  Dorit Shapira ,  Kosta Luria ,  Efraim Rotem

    IPC: G06F11/00 ,  G06F11/30 ,  G06F11/34

    CPC classification number: G06F11/3037 ,  G06F11/3419 ,  G06F11/3476 ,  G06F2201/88

    Abstract: In an embodiment, a processor includes measurement logic to measure a usage associated with the processor. The processor also includes statistical logic to determine, based on a statistical procedure, whether to provide a permission to record an increase in usage responsive to an indication that the usage has increased by a defined amount. The processor also includes control logic to record the defined increase in usage in non-volatile memory responsive to receipt of the permission to record from the statistical logic. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，处理器包括用于测量与处理器相关联的使用的测量逻辑。 处理器还包括用于基于统计过程来确定是否提供响应于使用已经增加了定义量的指示来记录使用增加的许可的统计逻辑。 处理器还包括控制逻辑，用于响应于从统计逻辑接收到记录的许可而记录在非易失性存储器中的定义的使用增加。 描述和要求保护其他实施例。

    Mapping A Performance Request To An Operating Frequency In A Processor
    52.
    发明申请
    Mapping A Performance Request To An Operating Frequency In A Processor 审中-公开
    将性能请求映射到处理器中的工作频率

    公开(公告)号：US20160259392A1

    公开(公告)日：2016-09-08

    申请号：US15135682

    申请日：2016-04-22

    Applicant: Intel Corporation

    Inventor： Eliezer Weissmann ,  Efraim Rotem ,  Paul Diefenbaugh ,  Guy Therien ,  Nir Rosenzweig

    IPC: G06F1/32

    CPC classification number: G06F1/324 ,  G06F1/3243 ,  G06F1/3293 ,  Y02D10/122 ,  Y02D10/126 ,  Y02D10/152

    Abstract: In an embodiment, a processor includes multiple cores each to independently execute instructions and a power control unit (PCU) coupled to the plurality of cores to control power consumption of the processor. The PCU may include a mapping logic to receive a performance scale value from an operating system (OS) and to calculate a dynamic performance-frequency mapping based at least in part on the performance scale value. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，处理器包括各自独立地执行指令的多个核心以及耦合到多个核心的功率控制单元（PCU），以控制处理器的功率消耗。 PCU可以包括映射逻辑以从操作系统（OS）接收性能标度值，并且至少部分地基于性能标度值来计算动态性能 - 频率映射。 描述和要求保护其他实施例。

    CONTROLLING A GUARANTEED FREQUENCY OF A PROCESSOR
    53.
    发明申请
    CONTROLLING A GUARANTEED FREQUENCY OF A PROCESSOR 有权
    控制处理器的保证频率

    公开(公告)号：US20160147275A1

    公开(公告)日：2016-05-26

    申请号：US14554628

    申请日：2014-11-26

    Applicant: Intel Corporation

    Inventor： Eliezer Weissmann ,  Hisham Abu Salah ,  Efraim Rotem ,  Guy M. Therien ,  Nadav Shulman ,  Esfir Natanzon ,  Paul S. Diefenbaugh

    IPC: G06F1/32 ,  G06F1/20

    CPC classification number: G06F1/3206 ,  G06F1/206 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

    Abstract: In one embodiment, a processor includes one or more cores to execute instructions and a power controller coupled to the one or more cores. In turn, the power controller includes a control logic to receive an indication, from one or more sources, of a dynamic change to a guaranteed frequency at which at least one of the one or more cores are to operate, and to determine a final guaranteed frequency at which the processor is to operate for a next window, and to communicate the final guaranteed frequency to at least one entity. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，处理器包括用于执行指令的一个或多个核和耦合到所述一个或多个核的功率控制器。 反过来，功率控制器包括控制逻辑，用于从一个或多个源接收动态变化到一个或多个核中的至少一个运行的保证频率的指示，以及确定最终保证 处理器要为下一个窗口操作的频率，以及将最终保证频率传送到至少一个实体。 描述和要求保护其他实施例。

    Techniques and system for managing platform temperature
    54.
    发明授权
    Techniques and system for managing platform temperature 有权
    平台温度管理技术和系统

    公开(公告)号：US09268378B2

    公开(公告)日：2016-02-23

    申请号：US13931128

    申请日：2013-06-28

    Applicant: Intel Corporation

    Inventor： Efraim Rotem ,  Alon Naveh ,  Doron Rajwan ,  Nadav Shulman ,  Eliezer Weissmann

    IPC: G06F1/20 ,  G06F1/32

    CPC classification number: G06F1/206 ,  G06F1/203 ,  G06F1/3206 ,  G06F1/3215 ,  G06F1/3243 ,  G06F1/3287 ,  Y02D10/16 ,  Y02D10/171 ,  Y02D50/20

    Abstract: In one embodiment an apparatus includes a temperature sensor to perform a multiplicity of junction temperature measurements for a component in a platform, a controller comprising logic at least a portion of which is in hardware. The logic may receive from the temperature sensor the multiplicity of junction temperature measurements and may instruct the component to perform a first power down action of the component when a junction temperature measurement exceeds a first threshold, and may instruct the component to perform a second power down action of the component when an average junction temperature based on the multiplicity of junction temperature measurements exceeds a second threshold. Other embodiments are disclosed and claimed.

    Abstract translation: 在一个实施例中，一种装置包括温度传感器，用于对平台中的部件执行多个结温测量，控制器包括至少其一部分处于硬件中的逻辑。 逻辑可以从温度传感器接收多个结温度测量值，并且当结温度测量超过第一阈值时可以指示组件执行部件的第一次掉电动作，并且可以指示组件执行第二次掉电 当基于结温度测量的多重性的平均结温超过第二阈值时，组分的作用。 公开和要求保护其他实施例。

    Method and apparatus of power management of processor
    57.
    发明授权
    Method and apparatus of power management of processor 有权
    处理器电源管理方法及装置

    公开(公告)号：US08874947B2

    公开(公告)日：2014-10-28

    申请号：US13893846

    申请日：2013-05-14

    Applicant: Intel Corporation

    Inventor： Efraim Rotem ,  Barnes Cooper ,  Guy Therien ,  Eliezer Weissmann ,  Anil Aggarwal

    IPC: G06F1/26 ,  G06F1/32

    CPC classification number: G06F1/3206 ,  G06F1/3203 ,  G06F1/3243 ,  Y02D10/152

    Abstract: A processing platform and a method of controlling power consumption of a central processing unit of the processing platform are presented. By operating the method the processing platform is able to set an upper performance state limit and a lower performance state limit. The upper performance state limit is based on a central processing unit activity rate value and the lower performance state limit is based on a minimum require of the operating system to perform operating system tasks. The performance state values are varying within a range of the lower and upper limits according to a power management policy.

    Abstract translation: 提出了处理平台和处理平台中央处理单元功耗控制方法。 通过操作该方法，处理平台能够设置较高的性能状态限制和较低的性能状态限制。 较高的性能状态限制基于中央处理单元活动速率值，较低的性能状态限制基于操作系统执行操作系统任务的最低要求。 性能状态值根据电源管理策略在下限和上限的范围内变化。

    DEVICE, METHOD, AND SYSTEM TO PROVIDE A LIMITED POWER STATES MODE FOR MANAGING PROCESSOR OPERATION
    58.
    发明申请
    DEVICE, METHOD, AND SYSTEM TO PROVIDE A LIMITED POWER STATES MODE FOR MANAGING PROCESSOR OPERATION 有权

    公开(公告)号：US20250004832A1

    公开(公告)日：2025-01-02

    申请号：US18216352

    申请日：2023-06-29

    Applicant: Intel Corporation

    Inventor： Yoav Babajani ,  Efraim Rotem ,  Gideon Reisfeld ,  Somvir Singh Dahiya ,  Yevgeni Sabin

    IPC: G06F9/48 ,  G06F1/26

    Abstract: Techniques and mechanisms for determining a mode by which a processor is to be transitioned between power states. In one embodiment, circuitry selectively transitions power management of the processor to or from a limited power states (LPS) mode which, as compared to an alternative power management mode, makes a relatively limited number of two or more power states available to the processor. A transition to or from the LPS mode is performed based on a thermal condition such as one which is based on a skin temperature of a housing structure in which the processor is disposed. In another embodiment, transitions between the two or more power states is performed, during the LPS mode, based on a pendency of a software workload, or based on a completion of such a software workload.

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