公开(公告)号：US20240405433A1

公开(公告)日：2024-12-05

申请号：US18328107

申请日：2023-06-02

Applicant: Intel Corporation

Inventor： Telesphor Kamgaing ,  Georg Seidemann ,  Harald Gossner ,  Thomas Wagner ,  Bernd Waidhas ,  Tae Young Yang

IPC: H01Q9/04 ,  H01Q1/22

Abstract: Disclosed herein are antenna modules, electronic assemblies, and communication devices. An example antenna module includes an IC component, an antenna patch support over a face of the IC component, and a stack of antenna patches vertically arranged at least partially above one another, where a first antenna patch of the stack is an antenna patch closest to the IC component, and a second antenna patch of the stack is an antenna patch closest to the first antenna patch. The first antenna patch is on the face of the IC component while the second and further antenna patches of the stack are on or in the antenna patch support and are electrically isolated from all electrically conductive material pathways in the antenna patch support and in the IC component.

公开(公告)号：US12057411B2

公开(公告)日：2024-08-06

申请号：US16721095

申请日：2019-12-19

Applicant: Intel Corporation

Inventor： Stephan Stoeckl ,  Wolfgang Molzer ,  Georg Seidemann ,  Bernd Waidhas

IPC: H01L23/58 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L49/02 ,  H01L23/00

CPC classification number: H01L23/585 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/3128 ,  H01L28/40 ,  H01L24/13 ,  H01L2221/68359 ,  H01L2221/68368 ,  H01L2224/0231 ,  H01L2224/02373 ,  H01L2224/13024

Abstract: Embodiments disclosed herein include semiconductor packages. In a particular embodiment, the semiconductor package is a wafer level chip scale package (WLCSP). In an embodiment, the WLCSP comprises a die. In an embodiment, the die comprises an active surface and a backside surface. The die has a first coefficient of thermal expansion (CTE). In an embodiment, the WLCSP further comprises a channel into the die. In an embodiment, the channel is filled with a stress relief material, where the stress relief material has a second CTE that is greater than the first CTE.

公开(公告)号：US20230317620A1

公开(公告)日：2023-10-05

申请号：US17708746

申请日：2022-03-30

Applicant: Intel Corporation

Inventor： Carlton Hanna ,  Georg Seidemann ,  Eduardo De Mesa ,  Abdallah Bacha ,  Lizabeth Keser

IPC: H01L23/538 ,  H01L23/15 ,  H01L25/065 ,  H01L21/48

CPC classification number: H01L23/5383 ,  H01L23/15 ,  H01L24/16 ,  H01L21/4857 ,  H01L25/0655

Abstract: Various embodiments disclosed relate to a semiconductor assembly having a ceramic or glass interposer for connecting dies within a semiconductor package. The present disclosure includes a ceramic or glass interposer having a carrier layer of substantially glass or ceramic material and a connecting layer having at least one dielectric layer and electrical routing therein.

公开(公告)号：US20230317582A1

公开(公告)日：2023-10-05

申请号：US17707183

申请日：2022-03-29

Applicant: Intel Corporation

Inventor： Carlton Hanna ,  Georg Seidemann ,  Eduardo De Mesa ,  Abdallah Bacha ,  Lizabeth Keser

IPC: H01L23/498 ,  H01L25/065 ,  H01L23/14 ,  H01L21/48 ,  H01L23/48

CPC classification number: H01L23/49822 ,  H01L23/49816 ,  H01L25/0655 ,  H01L23/145 ,  H01L23/5381 ,  H01L21/486 ,  H01L23/481 ,  H01L23/49838 ,  H01L2924/3511 ,  H01L21/4857

Abstract: An electronic device comprises a first redistribution layer (RDL) including multiple sublayers of conductive traces formed in an organic material; a stiffening layer including one of a ceramic or glass, the stiffening layer including a first surface contacting a first surface of the first RDL and including a through layer via (TLV); and multiple integrated circuit (ICs) arranged on a second surface of the first RDL and including bonding pads, wherein the conductive traces of the first RDL provide electrical continuity between at least one bonding pad of the ICs and at least one TLV of the stiffening layer.

公开(公告)号：US20230307313A1

公开(公告)日：2023-09-28

申请号：US17703400

申请日：2022-03-24

Applicant: Intel Corporation

Inventor： Carlton Hanna ,  Wolfgang Molzer ,  Stefan Reif ,  Georg Seidemann ,  Stephan Stoeckl ,  Pouya Talebbeydokhti

IPC: H01L23/373 ,  H01L23/367

CPC classification number: H01L23/3732 ,  H01L23/367

Abstract: A semiconductor package comprises a package substrate comprised of at least a first layer of dielectric material including a portion of diamond dust material. The diamond dust material is comprised of diamond dust particles. The semiconductor package includes at least one electrical connection coupled through layers of the package substrate.

公开(公告)号：US11735570B2

公开(公告)日：2023-08-22

申请号：US15945648

申请日：2018-04-04

Applicant: Intel Corporation

Inventor： David O'Sullivan ,  Georg Seidemann ,  Richard Patten ,  Bernd Waidhas

IPC: H01L25/10 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

CPC classification number: H01L25/105 ,  H01L21/486 ,  H01L21/4853 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L25/50 ,  H01L2224/214 ,  H01L2225/1035 ,  H01L2225/1058

Abstract: Embodiments include semiconductor packages and a method of forming the semiconductor packages. A semiconductor package includes a mold over and around a first die and a first via. The semiconductor package has a conductive pad of a first redistribution layer disposed on a top surface of the first die and/or a top surface of the mold. The semiconductor package includes a second die having a solder ball coupled to a die pad on a bottom surface of the second die, where the solder ball of the second die is coupled to the first redistribution layer. The first redistribution layer couples the second die to the first die, where the second die has a first edge and a second edge, and where the first edge is positioned within a footprint of the first die and the second edge is positioned outside the footprint of the first die.

公开(公告)号：US20220415815A1

公开(公告)日：2022-12-29

申请号：US17355770

申请日：2021-06-23

Applicant: Intel Corporation

Inventor： Bernd Waidhas ,  Carlton Hanna ,  Stephen Morein ,  Lizabeth Keser ,  Georg Seidemann

IPC: H01L23/538 ,  H01L23/48 ,  H01L23/00 ,  H01L25/16 ,  H05K1/18 ,  H01L25/065 ,  H01L25/18 ,  H01L23/367 ,  H01L25/00

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate including a first conductive pathway electrically coupled to a power source; a mold material on the package substrate including a first microelectronic component embedded in the mold material, a second microelectronic component embedded in the mold material, and a TMV, between the first and second microelectronic components, the TMV electrically coupled to the first conductive pathway; a redistribution layer (RDL) on the mold material including a second conductive pathway electrically coupled to the TMV; and a third microelectronic component on the RDL and electrically coupled to the second conductive pathway, wherein the second conductive pathway electrically couples the TMV, the first microelectronic component, and the third microelectronic component.

公开(公告)号：US20220310777A1

公开(公告)日：2022-09-29

申请号：US17213551

申请日：2021-03-26

Applicant: Intel Corporation

Inventor： David O'Sullivan ,  Georg Seidemann ,  Bernd Waidhas ,  Horst Baumeister

IPC: H01L49/02 ,  H01L23/498 ,  H01L25/065 ,  H01L25/00 ,  H01L21/48 ,  H01L23/00

Abstract: IC chip package routing structures including a metal-insulator-metal (MIM) capacitor integrated with redistribution layers. An active side of an IC chip may be electrically coupled to the redistribution layers through first-level interconnects. The redistribution layers terminate at interfaces suitable for coupling a package to a host component through second-level interconnects. The MIM capacitor structure may comprise materials suitable for high temperature processing, for example of 350° C., or more. The MIM capacitor structure may therefore be fabricated over a host substrate using higher temperature processing. The redistribution layers and MIM capacitor may then be embedded within package dielectric material(s) using lower temperature processing. An IC chip may be attached to the package routing structure, and the package then separated from the host substrate for further assembly to a host component.

公开(公告)号：US11270941B2

公开(公告)日：2022-03-08

申请号：US16349170

申请日：2016-12-29

Applicant: Intel Corporation

Inventor： Georg Seidemann ,  Thomas Wagner ,  Andreas Wolter ,  Bernd Waidhas

IPC: H01L23/528 ,  H01L23/00 ,  H01L25/065 ,  H01L21/768 ,  H01L23/48 ,  H01L23/532 ,  H01L23/538 ,  H01L25/16 ,  H01L21/56 ,  H01L23/498 ,  H01L23/31

Abstract: A system-in-package apparatus includes a semiconductive bridge that uses bare-die pillars to couple with a semiconductive device such as a processor die. The apparatus achieves a thin form factor.

公开(公告)号：US11107763B2

公开(公告)日：2021-08-31

申请号：US16469113

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Thomas Wagner ,  Andreas Wolter ,  Georg Seidemann

IPC: H01L23/522 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065

Abstract: A microelectronic package includes at least two semiconductor die, one die stacked over at least partially another. At a least the upper die is oriented with its active surface facing in the direction of a redistribution structure, and one or more wires are coupled to extend from contacts on that active surface into conductive structures in the redistribution structure.