公开(公告)号：US11211866B2

公开(公告)日：2021-12-28

申请号：US16642268

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： William J. Lambert ,  Kaladhar Radhakrishnan ,  Beomseok Choi ,  Krishna Bharath ,  Michael J. Hill

IPC: H02M3/158 ,  G01R19/165 ,  G05F1/46 ,  H01F21/02 ,  H02M1/00 ,  H02M3/156

Abstract: An adjustable inductance system includes a plurality of inductor modules coupled to a corresponding plurality of loads and a pool of at least one floating inductor module that may be coupled in parallel with any one of the plurality of inductor modules. A control circuit monitors the current drawn through the inductor module by the load. If current draw exceeds a threshold, the control circuit couples a floating inductor module to the load. Using the current drawn by the load, the control circuit determines an appropriate inductance value and determines an appropriate inductor configuration for the inductor module, the floating inductor module, or both the inductor module and the floating inductor module to achieve the determined inductance value. The control circuit causes switching elements to transition to a state or position to achieve the inductor configuration.

公开(公告)号：US20210305154A1

公开(公告)日：2021-09-30

申请号：US16829336

申请日：2020-03-25

Applicant: Intel Corporation

Inventor： Ying Wang ,  Yikang Deng ,  Junnan Zhao ,  Andrew James Brown ,  Cheng Xu ,  Kaladhar Radhakrishnan

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L49/02

Abstract: Disclosed herein are magnetic structures in integrated circuit (IC) package supports, as well as related methods and devices. For example, in some embodiments, an IC package support may include a conductive line, a magnetic structure around the conductive line, and material stubs at side faces of the magnetic structure.

公开(公告)号：US11081434B2

公开(公告)日：2021-08-03

申请号：US16993112

申请日：2020-08-13

Applicant: Intel Corporation

Inventor： Zhiguo Qian ,  Kaladhar Radhakrishnan ,  Kemal Aygun

IPC: H01L23/49 ,  H01L23/538 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L21/68

Abstract: The present disclosure is directed to systems and methods for improving the impedance matching of semiconductor package substrates by incorporating one or more magnetic build-up layers proximate relatively large diameter, relatively high capacitance, conductive pads formed on the lower surface of the semiconductor package substrate. The one or more magnetic layers may be formed using a magnetic build-up material deposited on the lower surface of the semiconductor package substrate. Vias conductively coupling the conductive pads to bump pads on the upper surface of the semiconductor package substrate pass through and are at least partially surrounded by the magnetic build-up material.

公开(公告)号：US20210183846A1

公开(公告)日：2021-06-17

申请号：US17185504

申请日：2021-02-25

Applicant: Intel Corporation

Inventor： Jeffory L. Smalley ,  Thomas Holden ,  Russell J. Wunderlich ,  Farzaneh Yahyaei-Moayyed ,  Mohanraj Prabhugoud ,  Horthense Delphine Tamdem ,  Vijaya Boddu ,  Kaladhar Radhakrishnan ,  Timothy Glen Hanna ,  Krishna Bharath ,  Judy Amanor-Boadu ,  Mark A. Schmisseur ,  Srikant Nekkanty ,  Luis E. Rosales Galvan

IPC: H01L25/18 ,  H01L23/498 ,  H01R12/71

Abstract: A processor module comprises an integrated circuit component attached to a power interposer. One or more voltage regulator modules attach to the power interposer via interconnect sockets and the power interposer routes regulated power signals generated by the voltage regulator modules to the integrated circuit component. Input power signals are provided to the voltage regulator from the system board via straight pins, a cable connector, or another type of connector. The integrated circuit component's I/O signals are routed through the power interposer to a system board via a socket located between the power interposer and the socket. Not having to route regulated power signals from a system board through a socket to an integrated circuit component can result in a system board with fewer layers, which can reduce overall system cost, as well as creating more area available in the remaining layers for I/O signal entry to the socket.

公开(公告)号：US20210098326A1

公开(公告)日：2021-04-01

申请号：US16498775

申请日：2017-04-28

Applicant: Intel Corporation

Inventor： Malavarayan Sankarasubramanian ,  Yongki Min ,  Ashay A. Dani ,  Kaladhar Radhakrishnan

IPC: H01L23/31 ,  H01L23/498 ,  H01L23/522

Abstract: A semiconductor package may include a composite magnetic inductor that is formed integral with the semiconductor substrate. The composite magnetic inductor may include a composite magnetic resin layer and a plurality of conductive layers arranged such that the composite magnetic resin layer is interleaved between successive conductive layers. The resultant composite magnetic inductor may be disposed between dielectric layers. A core layer may be disposed proximate the composite magnetic inductor. A build-up layer may be disposed proximate the core layer or proximate the composite magnetic inductor in a coreless semiconductor substrate. semiconductor die may couple to the build-up layer. The composite magnetic inductor beneficially provides a greater inductance than external inductors coupled to the semiconductor package.

公开(公告)号：US10741536B2

公开(公告)日：2020-08-11

申请号：US16426939

申请日：2019-05-30

Applicant: Intel Corporation

Inventor： Yongki Min ,  Reynaldo A. Olmedo ,  William J. Lambert ,  Kaladhar Radhakrishnan ,  Leigh E. Wojewoda ,  Venkat Anil K. Magadala ,  Clive R. Hendricks

IPC: H01L25/18 ,  H01F17/00 ,  H01L23/64 ,  H01L23/498 ,  H01L23/522 ,  H01L23/00 ,  H01L25/065 ,  H01L25/16

Abstract: An apparatus comprises an inductor module including: a module substrate including a magnetic dielectric material; a plurality of inductive circuit elements arranged in the module substrate, wherein an inductive circuit element includes conductive traces arranged as a coil including a first coil end, a second coil end and a coil core, wherein the coil core includes the magnetic dielectric material; and a plurality of conductive contact pads electrically coupled to the first and second coil ends. The contact pads electrically coupled to the first coil ends are arranged on a first surface of the inductor module, and the contact pads electrically coupled to the second coil ends are arranged on a second surface of the inductor module.

公开(公告)号：US20200251448A1

公开(公告)日：2020-08-06

申请号：US16635501

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： Beomseok Choi ,  Kaladhar Radhakrishnan ,  William Lambert ,  Michael Hill ,  Krishna Bharath

IPC: H01L25/065 ,  H01L23/528 ,  H01L23/522 ,  H01L25/00

Abstract: An apparatus is provided which comprises: a first set of one or more contacts on a first die surface, the first set of one or more contacts to couple with contacts of an integrated circuit die, one or more multi-level voltage clamps coupled with the first set of one or more contacts, the one or more multi-level voltage clamps switchable between two or more voltages, one or more integrated voltage regulators coupled with the one or more multi-level voltage clamps, the one or more integrated voltage regulators to provide an output voltage, one or more through silicon vias (TSVs) coupled with the one or more integrated voltage regulators, and a second set of one or more contacts on a second die surface, opposite the first die surface, the second set of one or more contacts coupled with the one or more TSVs, and the second set of one or more contacts to couple with contacts of a package substrate. Other embodiments are also disclosed and claimed.

公开(公告)号：US10453705B2

公开(公告)日：2019-10-22

申请号：US15865471

申请日：2018-01-09

Applicant: Intel Corporation

Inventor： Amit K. Jain ,  Sameer Shekhar ,  Kaladhar Radhakrishnan

IPC: H01L21/56 ,  H01F17/04 ,  H02J50/10 ,  H01F27/24 ,  H01L23/64 ,  H01L21/48 ,  H01F17/00 ,  H05K1/16 ,  H05K1/02

Abstract: Apparatuses and methods including an apparatus for an electronics package are disclosed. According to one embodiment, the apparatus can include one or more magnetic inductors, one or more capacitors positioned one of above or below to the one or more magnetic inductors and a plurality of electrical conductors comprising pillars. The pillars can extend substantially vertically to electrically connect the one or more magnetic inductors and the one or more capacitors to the electronics package and the one or more magnetic inductors, the one or more capacitors and the plurality of conductors are disposed one of above or below the electronics package; and at least one electrical conductor comprising a pillar extending substantially vertically to electrically connect the one or more magnetic inductors and the one or more capacitors.

公开(公告)号：US09230944B1

公开(公告)日：2016-01-05

申请号：US14464484

申请日：2014-08-20

Applicant: Intel Corporation

Inventor： William J. Lambert ,  Michael J. Hill ,  Kaladhar Radhakrishnan

IPC: H01L21/00 ,  H01L25/16 ,  H01L49/02 ,  H01L21/56 ,  H01L23/31 ,  H01L21/768 ,  H01L23/528 ,  H01G4/30 ,  H01G4/38

CPC classification number: H01G4/38 ,  H01G4/30 ,  H01L21/4846 ,  H01L23/49822 ,  H01L23/50 ,  H01L23/5227 ,  H01L23/5389 ,  H01L23/64 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L28/10 ,  H01L28/40 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15311 ,  H05K1/185 ,  H05K3/007 ,  H05K2201/1003 ,  H01L2924/014

Abstract: Embodiments of the present disclosure are directed toward techniques and configurations associated with a capductor assembly. In one embodiment, a capductor assembly may include a semiconductor wafer and a plurality of inductors disposed on a first side of the semiconductor wafer. The plurality of inductors may be embedded in electrically insulative material having a plurality of interconnect structures disposed thereon. The plurality of interconnect structures may be configured to electrically couple the plurality of inductors to a die. The IC assembly may further include a plurality of capacitors disposed on a second side of the wafer disposed opposite the first side of the wafer. The plurality of capacitors may be electrically coupled with a second plurality of interconnect structures that may be configured to electrically couple the plurality of capacitors with the die. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及与电感器组件相关联的技术和配置。 在一个实施例中，电感器组件可以包括半导体晶片和设置在半导体晶片的第一侧上的多个电感器。 多个电感器可以嵌入在其上布置有多个互连结构的电绝缘材料中。 多个互连结构可以被配置为将多个电感器电耦合到管芯。 IC组件还可以包括设置在与晶片的第一侧相对设置的晶片的第二侧上的多个电容器。 多个电容器可以与可被配置为将多个电容器与管芯电耦合的第二多个互连结构电耦合。 可以描述和/或要求保护其他实施例。