公开(公告)号：US20190303237A1

公开(公告)日：2019-10-03

申请号：US16448126

申请日：2019-06-21

Applicant: Intel Corporation

Inventor： Chetan Chauhan ,  Wei Wu ,  Rajesh Sundaram ,  Shigeki Tomishima

IPC: G06F11/10 ,  G06F11/07

Abstract: Technologies for preserving error correction capability in compute-near-memory operations in a memory include memory media and a media access circuitry coupled with the memory media. The media access circuitry is to detect an error code adjustment state indicative of a failure in the initiated error correction. The media access circuitry is to adjust a voltage to the memory media to eliminate the error code correction adjustment state. Once eliminated, the media access circuitry is to perform the error correction on the read data.

公开(公告)号：US20190227750A1

公开(公告)日：2019-07-25

申请号：US16370007

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Srikanth Srinivasan ,  Richard Coulson ,  Rajesh Sundaram ,  Bruce Querbach ,  Jawad B. Khan ,  Shigeki Tomishima ,  Sriram Vangal ,  Wei Wu ,  Chetan Chauhan

IPC: G06F3/06

Abstract: Technologies for performing tensor operations in memory include a memory comprising media access circuitry coupled to a memory media having a cross point architecture. The media access circuitry is to access matrix data from the memory media, perform a tensor operation on the matrix data, and write, to the memory media, resultant data indicative of a result of the tensor operation.

公开(公告)号：US10297302B2

公开(公告)日：2019-05-21

申请号：US15371122

申请日：2016-12-06

Applicant: Intel Corporation

Inventor： Charles Augustine ,  Shigeki Tomishima ,  Wei Wu ,  Shih-Lien Lu ,  James W. Tschanz ,  Georgios Panagopoulos ,  Helia Naeimi

IPC: G11C11/16

Abstract: An apparatus is described that includes a semiconductor chip memory array having resistive storage cells. The apparatus also includes a comparator to compare a first word to be written into the array against a second word stored in the array at the location targeted by a write operation that will write the first word into the array. The apparatus also includes circuitry to iteratively write to one or more bit locations where a difference exists between the first word and the second word with increasing write current intensity with each successive iteration.

公开(公告)号：US10095424B2

公开(公告)日：2018-10-09

申请号：US15228729

申请日：2016-08-04

Applicant: INTEL CORPORATION

Inventor： Wei Wu ,  Yi Zou ,  Jawad B. Khan ,  Xin Guo

IPC: G06F12/00 ,  G06F3/06 ,  G11C11/56 ,  G06F12/1009

Abstract: Provided are an apparatus, method, and system for programming a multi-cell storage cell group. A non-volatile memory has storage cells. Each storage cell is programmed with information using a plurality of threshold voltage levels and each storage cell is programmed from bits from a plurality of pages. A memory controller is configured to program the storage cells and to organize the storage cells in the non-volatile memory into storage cell groups. Each storage cell group stores a number of bits of information and each of the storage cells in each of the storage cell groups is programmed with the plurality of threshold voltage levels. The memory controller selects bits from the pages to write for one storage cell group and determines at least one threshold voltage level to use for each of the storage cells in the storage cell group to program the selected bits in the storage cell group.

公开(公告)号：US10083140B2

公开(公告)日：2018-09-25

申请号：US14975305

申请日：2015-12-18

Applicant: INTEL CORPORATION

Inventor： Wei Wu ,  Shigeki Tomishima ,  Shih-Lien L. Lu

IPC: G06F13/36 ,  G06F13/40 ,  G06F13/16 ,  G11C11/4091 ,  G11C11/4093 ,  G11C5/02 ,  G11C5/06 ,  G11C7/06 ,  G11C7/10

CPC classification number: G06F13/4022 ,  G06F13/1668 ,  G11C5/025 ,  G11C5/063 ,  G11C7/06 ,  G11C7/1048 ,  G11C11/4091 ,  G11C11/4093 ,  G11C2207/105 ,  G11C2207/107

Abstract: Provided are a memory device and a memory bank comprised of a local data bus, a segmented global data bus coupled to the local data bus, and a section select switch that is configurable to direct a signal from the local data bus to either end of the segmented global data bus. Provided also is a computational device comprising a processor and the memory device and optionally a display. Provided also is a method in which a signal is received from a local data bus, and a section select switch is configured to direct the signal from the local data bus to either end of a segmented global data bus.

公开(公告)号：US09654143B2

公开(公告)日：2017-05-16

申请号：US14308107

申请日：2014-06-18

Applicant: Intel Corporation

Inventor： Guillem Sole ,  Roger Espasa ,  Sorin Iacobovici ,  Brian Hickmann ,  Wei Wu ,  Thomas Fletcher

IPC: G06F11/10 ,  H03M13/09 ,  H03M13/17 ,  H03M13/19 ,  H03M13/29

CPC classification number: H03M13/09 ,  G06F11/1012 ,  H03M13/17 ,  H03M13/19 ,  H03M13/29

Abstract: Embodiments of an invention for consecutive bit error detection and correction are disclosed. In one embodiment, an apparatus includes a storage structure, a second storage structure, a parity checker, an error correction code (ECC) checker, and an error corrector. The first storage structure is to store a plurality of data values, a plurality of parity values, and a plurality of ECC values, each parity value corresponding to one of the plurality of data values, a first bit of each parity value corresponding to a first of a plurality of portions of a corresponding data value, wherein the first of the plurality of portions of the corresponding data value is interleaved with a second of the plurality of portions of the corresponding data value, wherein a second bit of each parity value corresponds to a second of the plurality of portions of the corresponding data value, each ECC value corresponding to one of the plurality of data values. The parity checker is to detect a parity error in a data value stored in the first storage structure using a parity value corresponding to the data value. The ECC checker is to generate a syndrome. The error corrector is to detect and correct consecutive bit errors in the data value using the syndrome.

公开(公告)号：US20160378591A1

公开(公告)日：2016-12-29

申请号：US14748826

申请日：2015-06-24

Applicant: Intel Corporation

Inventor： Helia Naeimi ,  Wei Wu ,  Shigeki Tomishima ,  Shih-Lien Lu

IPC: G06F11/10 ,  G11C11/16

CPC classification number: G06F11/1048 ,  G11C11/1673 ,  G11C11/1675 ,  G11C29/52 ,  G11C2029/0411

Abstract: Some embodiments include apparatuses and methods having an interface to receive information from memory cells, the memory cells configured to have a plurality of states to indicate values of information stored in the memory cells, and a control unit to monitor errors in information retrieved from the memory cells. Based on the errors in the information, the control unit generates control information to cause the memory cell to change to from a state among the plurality of states to an additional state. The additional state is different from the plurality of states.

Abstract translation: 一些实施例包括具有从存储器单元接收信息的接口的设备和方法，所述存储器单元被配置为具有多个状态以指示存储在存储器单元中的信息的值，以及控制单元，用于监视从存储器检索的信息中的错误 细胞。 基于信息中的错误，控制单元生成控制信息以使存储单元从多个状态之间的状态改变为附加状态。 附加状态与多个状态不同。

公开(公告)号：US20140218067A1

公开(公告)日：2014-08-07

申请号：US13997268

申请日：2013-01-16

Applicant: Intel Corporation

Inventor： Jiangtao Li ,  Patrick Koeberl ,  Sanu K. Mathew ,  Wei Wu

IPC: H03K19/177

CPC classification number: H03K19/17768 ,  G06F21/72 ,  H04L9/3247 ,  H04L9/3278

Abstract: A physically unclonable function (PUF) includes a plurality of PUF elements to generate an N-bit PUF signature. For each bit in the N-bit PUF signature, a PUF group of K number of individual PUF elements indicating a single-bit PUF value is used to generate a group bit. The group bits are more repeatable than the individual PUF elements. The value K may be selected such that (K+1)/2 is an odd number.

Abstract translation: 物理上不可克隆的功能（PUF）包括多个PUF元件以产生N位PUF签名。 对于N位PUF签名中的每个比特，使用指示单位PUF值的K个个体PUF元素的PUF组来生成组比特。 组位比PUF单个元件更可重复。 可以选择值K使得（K + 1）/ 2是奇数。