公开(公告)号：US20080200021A1

公开(公告)日：2008-08-21

申请号：US12104570

申请日：2008-04-17

申请人： Kevin K. Chan ,  Jia Chen ,  Shih-Fen Huang ,  Edward J. Nowak

发明人： Kevin K. Chan ,  Jia Chen ,  Shih-Fen Huang ,  Edward J. Nowak

IPC分类号： H01L21/3205

CPC分类号： H01L21/2807 ,  H01L21/28052 ,  H01L21/28061 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/4916 ,  H01L29/4925 ,  H01L29/665

摘要： A multi-layered gate electrode stack structure of a field effect transistor device is formed on a silicon nano crystal seed layer on the gate dielectric. The small grain size of the silicon nano crystal layer allows for deposition of a uniform and continuous layer of poly-SiGe with a [Ge] of up to at least 70% using in situ rapid thermal chemical vapor deposition (RTCVD). An in-situ purge of the deposition chamber in a oxygen ambient at rapidly reduced temperatures results in a thin SiO2 or SixGeyOz interfacial layer of 3 to 4A thick. The thin SiO2 or SixGeyOz interfacial layer is sufficiently thin and discontinuous to offer little resistance to gate current flow yet has sufficient [O] to effectively block upward Ge diffusion during heat treatment to thereby allow silicidation of the subsequently deposited layer of cobalt. The gate electrode stack structure is used for both nFETs and pFETs.

摘要翻译： 在栅极电介质上的硅纳米晶种子层上形成场效应晶体管器件的多层栅电极堆叠结构。 硅纳米晶体层的小晶粒尺寸允许使用原位快速热化学气相沉积（RTCVD）沉积高达至少70％的[Ge]的均匀且连续的多晶硅层。 在快速降低的温度下在氧气环境中原位吹扫沉积室导致薄的SiO 2或Si x O x O O 3至4A厚的界面层。 薄的SiO 2或Si x Si 2 O 3界面层足够薄且不连续以提供很小的电阻 到栅极电流仍具有足够的[O]以在热处理期间有效地阻挡Ge扩散，从而允许后续沉积的钴的硅化物。 栅电极堆叠结构用于nFET和pFET两者。

公开(公告)号：US07402466B2

公开(公告)日：2008-07-22

申请号：US11492271

申请日：2006-07-25

申请人： Kevin K. Chan ,  Meikei Ieong ,  Alexander Reznicek ,  Devendra K. Sadana ,  Leathen Shi ,  Min Yang

发明人： Kevin K. Chan ,  Meikei Ieong ,  Alexander Reznicek ,  Devendra K. Sadana ,  Leathen Shi ,  Min Yang

IPC分类号： H01L21/00

CPC分类号： H01L29/7842 ,  H01L21/2022 ,  H01L21/76275 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/78687

摘要： Methods of forming a strained Si-containing hybrid substrate are provided as well as the strained Si-containing hybrid substrate formed by the methods. In the methods of the present invention, a strained Si layer is formed overlying a regrown semiconductor material, a second semiconducting layer, or both. In accordance with the present invention, the strained Si layer has the same crystallographic orientation as either the regrown semiconductor layer or the second semiconducting layer. The methods provide a hybrid substrate in which at least one of the device layers includes strained Si.

摘要翻译： 提供了形成应变含Si的杂化基板的方法以及通过这些方法形成的应变的含Si杂化基板。 在本发明的方法中，形成覆盖重新生长的半导体材料，第二半导体层或两者的应变Si层。 根据本发明，应变Si层具有与再生长半导体层或第二半导电层相同的晶体取向。 该方法提供混合基板，其中至少一个器件层包括应变Si。

公开(公告)号：US07361611B2

公开(公告)日：2008-04-22

申请号：US11349233

申请日：2006-02-08

申请人： Ashima B. Chakravarti ,  Judson Holt ,  Kevin K. Chan ,  Sadanand V. Deshpande ,  Rangarajan Jagannathan

发明人： Ashima B. Chakravarti ,  Judson Holt ,  Kevin K. Chan ,  Sadanand V. Deshpande ,  Rangarajan Jagannathan

IPC分类号： H01L21/31

CPC分类号： H01L29/7843 ,  C23C16/308 ,  C23C16/34 ,  C23C16/401 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/3143 ,  H01L21/3144 ,  H01L21/3145 ,  H01L21/3148 ,  H01L21/31608 ,  H01L21/31612 ,  H01L21/3185 ,  H01L21/76801 ,  H01L21/76829 ,  H01L21/76834 ,  H01L29/7833 ,  H01L29/78675

摘要： Adding at least one non-silicon precursor (such as a germanium precursor, a carbon precursor, etc.) during formation of a silicon nitride, silicon oxide, silicon oxynitride or silicon carbide film improves the deposition rate and/or makes possible tuning of properties of the film, such as tuning of the stress of the film. Also, in a doped silicon oxide or doped silicon nitride or other doped structure, the presence of the dopant may be used for measuring a signal associated with the dopant, as an etch-stop or otherwise for achieving control during etching.

摘要翻译： 在形成氮化硅，氧化硅，氮氧化硅或碳化硅膜期间添加至少一种非硅前体（例如锗前体，碳前体等）改善了沉积速率和/或使得可以调谐性能 的电影，如调整电影的压力。 此外，在掺杂的氧化硅或掺杂氮化硅或其它掺杂结构中，掺杂剂的存在可用于测量与掺杂剂相关的信号，作为蚀刻停止或用于在蚀刻期间实现控制。

公开(公告)号：US07087965B2

公开(公告)日：2006-08-08

申请号：US10830347

申请日：2004-04-22

申请人： Kevin K. Chan ,  Meikei Ieong ,  Alexander Reznicek ,  Devendra K. Sadana ,  Leathen Shi ,  Min Yang

发明人： Kevin K. Chan ,  Meikei Ieong ,  Alexander Reznicek ,  Devendra K. Sadana ,  Leathen Shi ,  Min Yang

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392

CPC分类号： H01L29/7842 ,  H01L21/2022 ,  H01L21/76275 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/78687

摘要： Methods of forming a strained Si-containing hybrid substrate are provided as well as the strained Si-containing hybrid substrate formed by the methods. In the methods of the present invention, a strained Si layer is formed overlying a regrown semiconductor material, a second semiconducting layer, or both. In accordance with the present invention, the strained Si layer has the same crystallographic orientation as either the regrown semiconductor layer or the second semiconducting layer. The methods provide a hybrid substrate in which at least one of the device layers includes strained Si.

公开(公告)号：US06946696B2

公开(公告)日：2005-09-20

申请号：US10328285

申请日：2002-12-23

申请人： Kevin K. Chan ,  Guy M. Cohen ,  Meikei Ieong ,  Ronnen A. Roy ,  Paul Solomon ,  Min Yang

发明人： Kevin K. Chan ,  Guy M. Cohen ,  Meikei Ieong ,  Ronnen A. Roy ,  Paul Solomon ,  Min Yang

IPC分类号： H01L29/417 ,  H01L21/02 ,  H01L21/265 ,  H01L21/336 ,  H01L21/76 ,  H01L21/762 ,  H01L27/12 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786 ,  H01C27/148

CPC分类号： H01L29/66484 ,  H01L21/26533 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/7831 ,  H01L29/7834 ,  H01L29/78648

摘要： A double-gate field effect transistor (DGFET) structure and method of forming such a structure in which the parasitic capacitance under the source/drain regions is substantially reduced are provided. Two new means to reduce the parasitic capacitance under the source/drain regions are provided. Firstly, the silicon area outside the gate is converted to oxide while protecting a silicon ledge adjacent to the gate with a first spacer. The oxidation can be facilitated using a self-aligned oxygen implant, or implant of some other species. Secondly, the first spacer is removed, replaced with a second spacer, and a new silicon source/drain area is grown by employing lateral selective epi overgrowth and using the now exposed silicon ledge as a seed, over the self-aligned oxide isolation region. This achieves a low-capacitance to the back-plane, while retaining control of the threshold voltages.

摘要翻译： 提供了双栅场效应晶体管（DGFET）结构和形成这样的结构的方法，其中源/漏区下的寄生电容大大减小。 提供了两种降低源极/漏极区下寄生电容的新手段。 首先，栅极外部的硅区域被转换为氧化物，同时用第一间隔物保护邻近栅极的硅凸缘。 使用自对准氧植入物或某些其它物种的植入物可以促进氧化。 其次，去除第一间隔物，用第二间隔物代替，通过采用横向选择性外延生长并使用现在暴露的硅壁缘作为种子，在自对准氧化物隔离区域上生长新的硅源/漏区。 这实现了对背板的低电容，同时保持阈值电压的控制。

公开(公告)号：US06916694B2

公开(公告)日：2005-07-12

申请号：US10650400

申请日：2003-08-28

申请人： Hussein I. Hanafi ,  David J. Frank ,  Kevin K. Chan

发明人： Hussein I. Hanafi ,  David J. Frank ,  Kevin K. Chan

IPC分类号： H01L21/336 ,  H01L21/84

CPC分类号： H01L29/66545 ,  H01L29/665 ,  H01L29/66537 ,  H01L29/7842 ,  Y10S438/938

摘要： The present invention provides a method using a damascene-gate process to improve the transport properties of FETs through strain Si. Changes in mobility and FET characteristics are deliberately made in a Si or silicon-on-insulator (SOI) structure through the introduction of local strain in the channel region, without introducing strain in the device source and drain regions. The method has the advantage of not straining the source and drain regions resulting in very low leakage junctions and also it does not require any special substrate preparation like the case of a strained Si/relaxed SiGe system. Moreover, the method is compatible with existing mainstream CMOS processing. The present invention also provides a CMOS device that has a localized strained Si channel that is formed using the method of the present invention.

摘要翻译： 本发明提供了一种使用镶嵌栅极工艺来改善FET通过应变Si的传输特性的方法。 迁移率和FET特性的变化是通过在沟道区域中引入局部应变而在Si或绝缘体上硅（SOI）结构中作出的，而不会在器件源极和漏极区域引入应变。 该方法的优点是不会使源极和漏极区域产生非常低的泄漏接头，并且也不需要像应变Si /弛豫SiGe系统那样的任何特殊的衬底制备。 此外，该方法与现有的主流CMOS处理兼容。 本发明还提供一种CMOS器件，其具有使用本发明的方法形成的局部应变Si沟道。

公开(公告)号：US06841831B2

公开(公告)日：2005-01-11

申请号：US10461821

申请日：2003-06-13

申请人： Hussein I. Hanafi ,  Diane C. Boyd ,  Kevin K. Chan ,  Wesley Natzle ,  Leathen Shi

发明人： Hussein I. Hanafi ,  Diane C. Boyd ,  Kevin K. Chan ,  Wesley Natzle ,  Leathen Shi

IPC分类号： H01L21/336 ,  H01L29/786 ,  H01L29/76

CPC分类号： H01L29/78696 ,  H01L29/66545 ,  H01L29/66772 ,  H01L29/78612

摘要： A sub-0.05 μm channel length fully-depleted SOI MOSFET device having low source and drain resistance and minimal overlap capacitance and a method of fabricating the same are provided. The sub-0.05 μm channel length fully-depleted SOI MOSFET device includes an SOI structure which contains at least an SOI layer having a channel region of a first thickness and abutting source/drain regions of a second thickness present therein, wherein the second thickness is greater than the first thickness and the source/drain regions having a salicide layer present thereon. A gate region is present also atop the SOI layer.

摘要翻译： 提供了具有低源极和漏极电阻以及最小重叠电容的0.05微米通道长度的全耗尽SOI MOSFET器件及其制造方法。 子0.05通道长度全耗尽的SOI MOSFET器件包括SOI结构，其至少包含具有第一厚度的沟道区和邻接其中存在第二厚度的源极/漏极区的SOI层，其中第二厚度为 大于第一厚度，并且源/漏区具有存在于其上的自对准硅化物层。 栅极区也存在于SOI层的顶部。

公开(公告)号：US06821864B2

公开(公告)日：2004-11-23

申请号：US10093789

申请日：2002-03-07

申请人： Kevin K. Chan ,  Subhash B. Kulkarni ,  Gangadhara S. Mathad ,  Rajiv M. Ranade

发明人： Kevin K. Chan ,  Subhash B. Kulkarni ,  Gangadhara S. Mathad ,  Rajiv M. Ranade

IPC分类号： H01L2176

CPC分类号： H01L27/1087 ,  H01L21/3081 ,  H01L21/76224 ,  H01L21/76895

摘要： A method of forming at least one deep trench structure having an increased trench depth is provided. The method includes providing at least one deep trench having sidewalls that extend to a common bottom wall in a surface of a substrate. Each deep trench has initial dimensions that are wider than targeted dimensions for the deep trenches. To reduce the initial dimensions to that of the targeted dimensions, an epitaxial silicon film is formed selectively or non-selectively on at least some portions of the sidewalls using a low-temperature ultra-high vacuum epitaxial silicon growth tehnique.

摘要翻译： 提供了形成具有增加的沟槽深度的至少一个深沟槽结构的方法。 该方法包括提供至少一个具有延伸到衬底表面中的公共底壁的侧壁的深沟槽。 每个深沟槽的初始尺寸比深沟槽的目标尺寸宽。 为了将初始尺寸减小到目标尺寸的尺寸，使用低温超高真空外延硅生长技术在侧壁的至少一些部分上选择性地或非选择性地形成外延硅膜。

公开(公告)号：US06579614B2

公开(公告)日：2003-06-17

申请号：US09814766

申请日：2001-03-23

申请人： Kevin K. Chan ,  Erin C. Jones ,  Fenton R. McFeely ,  Paul M. Solomon ,  John J. Yurkas

发明人： Kevin K. Chan ,  Erin C. Jones ,  Fenton R. McFeely ,  Paul M. Solomon ,  John J. Yurkas

IPC分类号： B32B900

CPC分类号： C23C16/56 ,  H01L21/28008 ,  H01L21/32053 ,  H01L21/3211 ,  H01L29/4908 ,  Y10T428/12576 ,  Y10T428/12583 ,  Y10T428/12674 ,  Y10T428/1284 ,  Y10T428/265

摘要： A method of treating structures (and the structure formed thereby), so as to prevent or retard the oxidation of a metal film, and/or prevent its delamination a substrate, includes providing a structure including a refractory metal film formed on a substrate, placing the structure into a vessel having a base pressure below approximately 10−7 torr, exposing the structure to a silane gas at a sufficiently high predetermined temperature and predetermined pressure to cause formation of a metal silicide layer on the refractory metal film, and exposing the structure to a second gas at a sufficiently high temperature and pressure to nitride the metal silicide layer into a nitrided layer.

摘要翻译： 一种处理结构（及其形成的结构）的方法，以防止或延缓金属膜的氧化和/或防止其基板的分层，包括提供包括在基板上形成的难熔金属膜的结构，放置 将结构转换成基本压力低于约10 -7乇的容器，将结构暴露于足够高的预定温度和预定压力下的硅烷气体，以在难熔金属膜上形成金属硅化物层，并使结构暴露 以足够高的温度和压力将第二气体氮化成氮化层。

公开(公告)号：US5565031A

公开(公告)日：1996-10-15

申请号：US390132

申请日：1995-02-17

申请人： Cyril Cabral, Jr. ,  Kevin K. Chan ,  Jack O. Chu ,  James M. E. Harper

发明人： Cyril Cabral, Jr. ,  Kevin K. Chan ,  Jack O. Chu ,  James M. E. Harper

IPC分类号： C30B29/06 ,  C23C14/08 ,  C23C16/04 ,  H01L21/20 ,  H01L21/203 ,  H01L21/205

CPC分类号： H01L21/02642 ,  H01L21/02373 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02631 ,  Y10S148/106 ,  Y10S438/945

摘要： Epitaxial and polycrystalline layers of silicon and silicon-germanium alloys are selectively grown on a semiconductor substrate or wafer by forming over the wafer a thin film masking layer of an oxide of an element selected from scandium, yttrium, lanthanum, cerium, praseodymium, neodymium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, and lutetium; and then growing the epitaxial layer over the wafer at temperatures below 650.degree. C. The epitaxial and polycrystalline layers do not grow on the masking layer. The invention overcomes the problem of forming epitaxial layers at temperatures above 650.degree. C. by providing a lower temperature process.

摘要翻译： 通过在晶片上形成选自钪，钇，镧，铈，镨，钕，钕，钕等的元素的氧化物的薄膜掩蔽层，选择性地在半导体衬底或晶片上生长硅和硅 - 锗合金的外延和多晶层， 钐，铕，钆，铽，镝，钬，铒，ium，镱和镥; 然后在低于650℃的温度下在晶片上生长外延层。外延层和多晶层不会在掩模层上生长。 本发明克服了通过提供较低温度的工艺在高于650℃的温度下形成外延层的问题。