公开(公告)号：US08738879B2

公开(公告)日：2014-05-27

申请号：US13608605

申请日：2012-09-10

申请人： Hong Beom Pyeon ,  Hakjune Oh ,  Jin-Ki Kim

发明人： Hong Beom Pyeon ,  Hakjune Oh ,  Jin-Ki Kim

IPC分类号： G06F12/00 ,  G06F13/40

CPC分类号： G06F13/4022 ,  G11C7/1048 ,  G11C7/18 ,  G11C11/408

摘要： Provided is a memory system that has a plurality of memory banks and a plurality of link controllers. For each memory bank, there is first switching logic for receiving output for each link controller, and for passing on the output of only one of the link controllers to the memory bank. For each link controller, there is second switching logic for receiving an output of each memory bank, and for passing on the output of only one of the memory banks to the link controller. According to an embodiment of the invention, there is switch controller logic for controlling operation of both the first switching logic and the second switching logic to prevent simultaneous or overlapping access by multiple link controllers to the same memory bank, and for preventing simultaneous or overlapping access to multiple banks by the same link controller.

摘要翻译： 提供了具有多个存储体和多个链接控制器的存储器系统。 对于每个存储体，存在用于接收每个链路控制器的输出并且仅将一个链路控制器的输出传递到存储体的第一切换逻辑。 对于每个链路控制器，存在用于接收每个存储体的输出并且仅将一个存储体的输出传递到链路控制器的第二切换逻辑。 根据本发明的实施例，存在用于控制第一开关逻辑和第二开关逻辑的操作的开关控制器逻辑，以防止多个链路控制器同时或重叠地访问同一存储体，并且用于防止同时或重叠访问 通过相同的链路控制器到多个银行。

公开(公告)号：US08549250B2

公开(公告)日：2013-10-01

申请号：US13590795

申请日：2012-08-21

申请人： Hong Beom Pyeon ,  HakJune Oh ,  Jin-Ki Kim

发明人： Hong Beom Pyeon ,  HakJune Oh ,  Jin-Ki Kim

IPC分类号： G06F12/00 ,  G06F3/00

CPC分类号： G06F13/4243 ,  G06F12/0676

摘要： A plurality of memory devices of mixed type (e.g., DRAMs, SRAMs, MRAMs and NAND-, NOR- and AND-type Flash memories) having associated device type information is serially interconnected. A serial input (SI) containing a device type (DT) and a device identifier (ID) is fed to one device of the serial interconnection. Upon a match between the fed DT matches the DT of the device, the fed ID is latched in a register of the device and an ID for another device is generated, which is then transferred to the next device in the serial interconnection. Otherwise, ID generation is skipped. These steps are performed in all devices. Thus, sequential IDs are generated for the different device types and also the total number of each device type is recognized. If the fed DT is “don't care”, sequential IDs are generated for all devices and the total number of the devices is recognized.

摘要翻译： 具有相关联的设备类型信息的多种混合型存储器件（例如，DRAM，SRAM，MRAM和NAND，NOR和AND型闪存）被串联连接。 包含设备类型（DT）和设备标识符（ID）的串行输入（SI）被馈送到串行互连的一个设备。 在馈送的DT匹配设备的DT之间匹配时，馈送的ID被锁存在设备的寄存器中，并且生成另一个设备的ID，然后将其传送到串行互连中的下一个设备。 否则，跳过ID生成。 这些步骤在所有设备中执行。 因此，为不同的设备类型生成顺序ID，并且还识别每个设备类型的总数。 如果馈送的DT是“不关心”，则为所有设备生成连续的ID，并识别设备的总数。

公开(公告)号：US08407395B2

公开(公告)日：2013-03-26

申请号：US11843440

申请日：2007-08-22

申请人： Jin-Ki Kim ,  HakJune Oh ,  Hong Beom Pyeon ,  Steven Przybylski

发明人： Jin-Ki Kim ,  HakJune Oh ,  Hong Beom Pyeon ,  Steven Przybylski

IPC分类号： G06F12/00

CPC分类号： G11C7/1042 ,  G06F12/0623 ,  G06F13/1694 ,  G06F13/4256 ,  G11C7/10 ,  G11C7/22 ,  G11C16/06 ,  G11C16/10 ,  G11C2216/30 ,  Y02D10/14 ,  Y02D10/151

摘要： A memory system architecture has serially connected memory devices. The memory system is scalable to include any number of memory devices without any performance degradation or complex redesign. Each memory device has a serial input/output interface for communicating between other memory devices and a memory controller. The memory controller issues commands in at least one bitstream, where the bitstream follows a modular command protocol. The command includes an operation code with optional address information and a device address, so that only the addressed memory device acts upon the command. Separate data output strobe and command input strobe signals are provided in parallel with each output data stream and input command data stream, respectively, for identifying the type of data and the length of the data. The modular command protocol is used for executing concurrent operations in each memory device to further improve performance.

摘要翻译： 存储器系统架构具有串行连接的存储器件。 内存系统具有可扩展性，可以包含任何数量的内存设备，而不会造成任何性能下降或重新设计。 每个存储器件具有用于在其他存储器件和存储器控制器之间进行通信的串行输入/输出接口。 存储器控制器在至少一个比特流中发出命令，其中比特流遵循模块化命令协议。 该命令包括具有可选地址信息和设备地址的操作代码，使得只有寻址的存储器件对该命令起作用。 分别提供与每个输出数据流和输入命令数据流并行提供的数据输出选通信号和命令输入选通信号，用于识别数据的类型和数据的长度。 模块化命令协议用于在每个存储设备中执行并发操作，以进一步提高性能。

公开(公告)号：US08407371B2

公开(公告)日：2013-03-26

申请号：US13077168

申请日：2011-03-31

申请人： Hong Beom Pyeon ,  HakJune Oh ,  Jin-Ki Kim ,  Shuji Sumi

发明人： Hong Beom Pyeon ,  HakJune Oh ,  Jin-Ki Kim ,  Shuji Sumi

IPC分类号： G06F3/00

摘要： A plurality of memory devices of mixed type (e.g., DRAMs, SRAMs, MRAMs and NAND-, NOR- and AND-type Flash memories) are serially interconnected. Each device has device type information on its device type. A specific device type (DT) and a device identifier (ID) contained in a serial input (SI) are fed to one device of the serial interconnection. The device determines whether the fed DT matches the DT of the device. In a case of match, a calculator included in the device performs calculation to generate an ID for another device and the fed ID is latched in a register of the device. The generated ID is transferred to another device of the serial interconnection. In a case of no match, the ID generation is skipped and no ID is generated for another device. Such a device type match determination and ID generation or skip are performed in all devices of the serial interconnection. In cases of different device types being separately provided to the interconnected devices, sequential IDs are generated in each of the different device types and also the total number of each device type are recognized. In a case of a “don't care” code is provided to the interconnected devices, sequential IDs are generated and also, the total number of the interconnected devices is recognized, regardless of the type differences.

公开(公告)号：US08399973B2

公开(公告)日：2013-03-19

申请号：US12168354

申请日：2008-07-07

申请人： HakJune Oh ,  Jin-Ki Kim ,  Hong Beom Pyeon

发明人： HakJune Oh ,  Jin-Ki Kim ,  Hong Beom Pyeon

IPC分类号： H01L23/02 ,  H01L23/48

CPC分类号： G11C5/06 ,  G11C5/02 ,  G11C5/04 ,  H01L23/481 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49113 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/20752 ,  H01L2924/00015

摘要： A first memory device and second memory device have a same input/output layout configuration. To form a stack, the second memory device is secured to the first memory device. To facilitate connectivity, the second memory device is rotationally offset with respect to the first memory device in the stack to align outputs of the first memory device with corresponding inputs of the second memory device. The rotational offset of the second memory device with respect to the first memory device aligns one or more outputs of the first memory device with one or more respective inputs of the second memory device. Based on links between outputs and inputs from one memory device to another in the stack, the stack of memory devices can include paths facilitating one or more series connection configurations through he memory devices.

摘要翻译： 第一存储器件和第二存储器件具有相同的输入/输出布局配置。 为了形成堆叠，第二存储器件被固定到第一存储器件。 为了便于连接，第二存储器设备相对于堆叠中的第一存储器设备旋转偏移，以使第一存储器件的输出与第二存储器件的相应输入相对准。 第二存储器件相对于第一存储器件的旋转偏移将第一存储器件的一个或多个输出与第二存储器件的一个或多个相应的输入对准。 基于输出和来自堆叠中的一个存储器设备的输入之间的链接，存储器件堆可以包括通过其存储器件便于一个或多个串联连接配置的路径。

公开(公告)号：US08295115B2

公开(公告)日：2012-10-23

申请号：US13072097

申请日：2011-03-25

申请人： Jin-Ki Kim ,  HakJune Oh

发明人： Jin-Ki Kim ,  HakJune Oh

IPC分类号： G11C7/00

CPC分类号： G11C11/40615 ,  G11C11/406 ,  G11C11/40607 ,  G11C11/40618 ,  G11C11/40622

摘要： A dynamic random access memory device includes a plurality of memory subblocks. Each subblock has a plurality of wordlines whereto a plurality of data store cells are connected. Partial array self-refresh (PASR) configuration settings are independently made. In accordance with the PASR settings, the memory subblocks are addressed for refreshing. The PASR settings are made by a memory controller. Any kind of combinations of subblock addresses may be selected. Thus, the memory subblocks are fully independently refreshed. User selectable memory arrays for data retention provide effective memory control programming especially for low power mobile application.

摘要翻译： 动态随机存取存储器件包括多个存储器子块。 每个子块具有连接多个数据存储单元的多个字线。 部分阵列自刷新（PASR）配置设置是独立制作的。 根据PASR设置，内存子块被寻址以进行刷新。 PASR设置由内存控制器进行。 可以选择子块地址的任何种类的组合。 因此，存储器子块被完全独立地刷新。 用于数据保留的用户可选择的存储器阵列提供有效的存储器控​​制编程，特别是对于低功率移动应用。

公开(公告)号：US08195839B2

公开(公告)日：2012-06-05

申请号：US12892215

申请日：2010-09-28

申请人： Hong Beom Pyeon ,  HakJune Oh ,  Jin-Ki Kim ,  Shuji Sumi

发明人： Hong Beom Pyeon ,  HakJune Oh ,  Jin-Ki Kim ,  Shuji Sumi

IPC分类号： G06F3/00

CPC分类号： G11C7/1078 ,  G11C7/1051 ,  G11C7/1063 ,  G11C7/109

摘要： A method and apparatus for assigning a device identifier for a plurality of devices of mixed type (e.g., DRAMs, SRAMs, MRAMs, and NAND-, NOR- and AND-type Flash memories) in a serial interconnection configuration are disclosed. One device of the serial interconnection configuration receives a device identifier (ID) and a device type (DT) as a packet through its serial input connection. A first determination is performed as to whether the DT of the device contains pre-defined data corresponding to one including all device types to provide a first determination result; and a second determination of the DT of the device is performed in response to the received DT to provide a second determination result. An ID is produced and output to a next device in response to the first and second determination results. The received ID or the produced ID is assigned to the respective devices.

摘要翻译： 公开了一种在串行互连配置中为多个混合类型的设备（例如，DRAM，SRAM，MRAM，以及NAND，NOR和AND型闪存）分配设备标识符的方法和装置。 串行互连配置的一个设备通过其串行输入连接接收设备标识符（ID）和设备类型（DT）作为数据包。 执行关于设备的DT是否包含对应于包括所有设备类型的预定数据以提供第一确定结果的第一确定; 并且响应于接收的DT执行设备的DT的第二确定，以提供第二确定结果。 响应于第一和第二确定结果产生ID并将其输出到下一个设备。 所接收的ID或产生的ID被分配给各个设备。

公开(公告)号：US07945755B2

公开(公告)日：2011-05-17

申请号：US12757406

申请日：2010-04-09

申请人： Hong Beom Pyeon ,  Hakjune Oh ,  Jin-Ki Kim

发明人： Hong Beom Pyeon ,  Hakjune Oh ,  Jin-Ki Kim

IPC分类号： G06F12/00

CPC分类号： G06F13/4022 ,  G11C7/1048 ,  G11C7/18 ,  G11C11/408

摘要： Provided is a memory system that has a plurality of memory banks and a plurality of link controllers. For each memory bank, there is first switching logic for receiving output for each link controller, and for passing on the output of only one of the link controllers to the memory bank. For each link controller, there is second switching logic for receiving an output of each memory bank, and for passing on the output of only one of the memory banks to the link controller. According to an embodiment of the invention, there is switch controller logic for controlling operation of both the first switching logic and the second switching logic to prevent simultaneous or overlapping access by multiple link controllers to the same memory bank, and for preventing simultaneous or overlapping access to multiple banks by the same link controller.

摘要翻译： 提供了具有多个存储体和多个链接控制器的存储器系统。 对于每个存储体，存在用于接收每个链路控制器的输出并且仅将一个链路控制器的输出传递到存储体的第一切换逻辑。 对于每个链路控制器，存在用于接收每个存储体的输出并且仅将一个存储体的输出传递到链路控制器的第二切换逻辑。 根据本发明的实施例，存在用于控制第一开关逻辑和第二开关逻辑的操作的开关控制器逻辑，以防止多个链路控制器同时或重叠地访问同一存储体，并且用于防止同时或重叠访问 通过相同的链路控制器到多个银行。

公开(公告)号：US07826294B2

公开(公告)日：2010-11-02

申请号：US12275701

申请日：2008-11-21

申请人： HakJune Oh ,  Hong Beom Pyeon ,  Jin-Ki Kim

发明人： HakJune Oh ,  Hong Beom Pyeon ,  Jin-Ki Kim

IPC分类号： G11C7/00

CPC分类号： G11C11/5628 ,  G06F1/12 ,  G11C7/1021 ,  G11C7/1051 ,  G11C7/1078 ,  G11C11/5642 ,  G11C16/06 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3445 ,  G11C2207/107

摘要： An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

摘要翻译： 公开了一种用于控制向半导体存储器中的串行数据链路接口的输出端口传送数据的装置，系统和方法。 在一个示例中，闪存设备可以具有多个串行数据链路，多个存储器组和控制输入端口，其使得存储器设备能够将串行数据传送到存储器件的串行数据输出端口。 在另一示例中，闪存器件可以具有单个串行数据链路，单个存储体，串行数据输入端口，用于接收输出使能信号的控制输入端口。 闪存器件可以使用回波信号线以菊花链配置级联以在存储器件之间串行通信。

公开(公告)号：US07529149B2

公开(公告)日：2009-05-05

申请号：US11637175

申请日：2006-12-12

申请人： Hong Beom Pyeon ,  HakJune Oh ,  Jin-Ki Kim

发明人： Hong Beom Pyeon ,  HakJune Oh ,  Jin-Ki Kim

IPC分类号： G11C8/00

CPC分类号： G11C7/1045 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1075 ,  G11C7/1078 ,  G11C2207/107

摘要： Methods and systems are provided that allow the method of access to one or more memory banks to be performed using serial access, or using parallel access. In serial mode, each link operates as an independent serial link. In contrast, during serial mode, the links operate in common as a parallel link. Where input and output controls are received independently for each link for serial mode, a single set of input and output controls is used in common by all of the links during parallel mode.

摘要翻译： 提供了允许使用串行访问或使用并行访问来执行访问一个或多个存储体的方法和系统。 在串行模式下，每个链路都作为一个独立的串行链路运行。 相比之下，在串行模式下，链路作为并行链路共同工作。 在为串行模式的每个链路独立接收输入和输出控制的情况下，在并行模式期间，所有链路都使用一组输入和输出控制。