公开(公告)号：US07018882B2

公开(公告)日：2006-03-28

申请号：US10807931

申请日：2004-03-23

申请人： Douglas J. Tweet ,  Sheng Teng Hsu ,  Jer-Shen Maa

发明人： Douglas J. Tweet ,  Sheng Teng Hsu ,  Jer-Shen Maa

IPC分类号： H01L21/8238 ,  H01L21/336

CPC分类号： H01L29/1054 ,  H01L21/823807 ,  H01L29/78

摘要： A method of forming a substrate for use in IC device fabrication includes preparing a silicon substrate, including doping a bulk silicon (100) substrate with ions taken from the group of ions to form a doped substrate taken from the group of doped substrates consisting of n-type doped substrates and p-type doped substrates; forming a first relaxed SiGe layer on the silicon substrate; forming a first tensile-strained silicon cap on the first relaxed SiGe layer; forming a second relaxed SiGe layer on the first tensile-strained silicon cap; forming a second tensile-strained silicon cap on the second relaxed SiGe layer; and completing an IC device.

摘要翻译： 一种形成用于IC器件制造的衬底的方法包括制备硅衬底，其包括用从离子组中取出的离子掺杂体硅（100）衬底，以形成从由n组成的掺杂衬底组中取出的掺杂衬底 型掺杂衬底和p型掺杂衬底; 在硅衬底上形成第一弛豫的SiGe层; 在第一松弛SiGe层上形成第一拉伸应变硅帽; 在第一拉伸应变硅帽上形成第二松弛SiGe层; 在第二松弛SiGe层上形成第二拉伸应变硅帽; 并完成IC设备。

公开(公告)号：US07378309B2

公开(公告)日：2008-05-27

申请号：US11376542

申请日：2006-03-15

申请人： Jong-Jan Lee ,  Paul J. Schuele ,  Sheng Teng Hsu ,  Jer-Shen Maa

发明人： Jong-Jan Lee ,  Paul J. Schuele ,  Sheng Teng Hsu ,  Jer-Shen Maa

IPC分类号： H01L21/8234

CPC分类号： H01L21/823871 ,  H01L21/02532 ,  H01L21/02667 ,  H01L21/28525 ,  H01L21/76895 ,  H01L27/11 ,  H01L27/1108

摘要： A method of fabricating local interconnect on a silicon-germanium 3D CMOS includes fabricating an active silicon CMOS device on a silicon substrate. An insulator layer is deposited on the silicon substrate and a seed window is opened through the insulator layer to the silicon substrate and to a silicon CMOS device gate. A germanium thin film is deposited on the insulator layer and into windows, forming a contact between the germanium thin film and the silicon device. The germanium thin film is encapsulated in a dielectric material. The wafer is heated at a temperature sufficient to flow the germanium, while maintaining the other layers in a solid condition. The wafer is cooled to solidify the germanium as single crystal germanium and as polycrystalline germanium, which provides local interconnects. Germanium CMOS devices may be fabricated on the single crystal germanium thin film.

摘要翻译： 在硅 - 锗3D CMOS上制造局部互连的方法包括在硅衬底上制造有源硅CMOS器件。 绝缘体层沉积在硅衬底上，并且晶种窗通过绝缘体层向硅衬底和硅CMOS器件栅极打开。 在绝缘体层和窗口上沉积锗薄膜，形成锗薄膜和硅器件之间的接触。 锗薄膜被封装在电介质材料中。 在足以使锗流动的温度下加热晶片，同时将其它层保持在固体状态。 将晶片冷却以将锗固化为单晶锗和作为多晶锗，其提供局部互连。 可以在单晶锗薄膜上制造锗CMOS器件。

公开(公告)号：US07226504B2

公开(公告)日：2007-06-05

申请号：US10062336

申请日：2002-01-31

申请人： Jer-Shen Maa ,  Douglas James Tweet ,  Tingkai Li ,  Jong-Jan Lee ,  Sheng Teng Hsu

发明人： Jer-Shen Maa ,  Douglas James Tweet ,  Tingkai Li ,  Jong-Jan Lee ,  Sheng Teng Hsu

IPC分类号： C30B33/02

CPC分类号： H01L21/3247 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02694 ,  H01L21/324

摘要： A method of forming a SiGe layer having a relatively high germanium content and a relatively low threading dislocation density includes preparing a silicon substrate; depositing a layer of SiGe to a thickness of between about 100 nm to 500 nm, wherein the germanium content of the SiGe layer is greater than 20%, by atomic ratio; implanting H+ ions into the SiGe layer at a dose of between about 1·1016 cm−2 to 5·1016 cm−2, at an energy of between about 20 keV to 45 keV; patterning the SiGe layer with photoresist; plasma etching the structure to form trenches about regions; removing the photoresist; and thermal annealing the substrate and SiGe layer, to relax the SiGe layer, in an inert atmosphere at a temperature of between about 650° C. to 950° C. for between about 30 seconds and 30 minutes.

摘要翻译： 形成具有较高锗含量和较低穿透位错密度的SiGe层的方法包括制备硅衬底; 将SiGe层沉积至约100nm至500nm的厚度，其中SiGe层的锗含量按原子比大于20％; 将H +离子以约1.10×16cm -2至0.0010±0.2cm的剂量注入SiGe层中， SUP>，在约20keV至45keV之间的能量; 用光致抗蚀剂图案化SiGe层; 等离子体蚀刻结构以形成关于区域的沟槽; 去除光致抗蚀剂; 以及对基板和SiGe层进行热退火，以在惰性气氛中在约650℃至950℃的温度下放置SiGe层约30秒至30分钟。

公开(公告)号：US07176072B2

公开(公告)日：2007-02-13

申请号：US11046411

申请日：2005-01-28

申请人： Jong-Jan Lee ,  Jer-Shen Maa ,  Sheng Teng Hsu

发明人： Jong-Jan Lee ,  Jer-Shen Maa ,  Sheng Teng Hsu

IPC分类号： H01L21/84 ,  H01L21/00 ,  H01L21/658

CPC分类号： H01L27/1266 ,  H01L27/1203 ,  H01L27/1214 ,  H01L29/78687

摘要： A method of fabricating strained silicon devices for transfer to glass for display applications includes preparing a wafer having a silicon substrate thereon; forming a relaxed SiGe layer on the silicon substrate; forming a strained silicon layer on the relaxed SiGe layer; fabricating an IC device on the strained silicon layer; depositing a dielectric layer on the wafer to cover a gate module of the IC device; smoothing the dielectric; implanting ions to form a defect layer; cutting the wafer into individual silicon dies; preparing a glass panel and the silicon dies for bonding; bonding the silicon dies onto the glass panel to form a bonded structure; annealing the bonded structure; splitting the bonded structure along the defect layer; removing the remaining silicon layer from the silicon substrate and relaxed SiGe layer on the silicon die on the glass panel; and completing the glass panel circuitry.

摘要翻译： 制造用于转移到用于显示器应用的玻璃的应变硅器件的方法包括制备其上具有硅衬底的晶片; 在硅衬底上形成松弛的SiGe层; 在松弛的SiGe层上形成应变硅层; 在应变硅层上制造IC器件; 在所述晶片上沉积介电层以覆盖所述IC器件的栅极模块; 平滑电介质; 注入离子以形成缺陷层; 将晶片切割成单独的硅模具; 制备玻璃面板和用于接合的硅模具; 将硅模具接合到玻璃面板上以形成接合结构; 退火键合结构; 沿着缺陷层分离粘结结构; 从硅衬底去除剩余的硅层并在玻璃面板上的硅晶片上松弛SiGe层; 并完成玻璃面板电路。

公开(公告)号：US07514282B2

公开(公告)日：2009-04-07

申请号：US11649634

申请日：2007-01-04

申请人： Tingkai Li ,  Jong-Jan Lee ,  Jer-Shen Maa ,  Sheng Teng Hsu

发明人： Tingkai Li ,  Jong-Jan Lee ,  Jer-Shen Maa ,  Sheng Teng Hsu

IPC分类号： H01L21/00

CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L21/306 ,  H01L29/0669 ,  H01L29/0673 ,  Y10S977/743

摘要： An array of submicron silicon (Si) tubes is provided with a method for patterning submicron Si tubes. The method provides a Si substrate, and forms a silicon dioxide film overlying the Si substrate. An array of silicon dioxide rods is formed from the silicon dioxide film, and Si3N4 tubes are formed surrounding the silicon dioxide rods. The silicon dioxide rods are etched away. Then, exposed regions of the Si substrate are etched, forming Si tubes underlying the Si3N4 tubes. Finally, the Si3N4 tubes are removed.

摘要翻译： 亚微米硅（Si）管的阵列具有用于构图亚微米Si管的方法。 该方法提供Si衬底，并形成覆盖Si衬底的二氧化硅膜。 由二氧化硅膜形成二氧化硅棒阵列，在二氧化硅棒周围形成Si 3 N 4管。 二氧化硅棒被蚀刻掉。 然后，蚀刻Si衬底的暴露区域，形成Si 3 N 4管下面的Si管。 最后，去除Si3N4管。

公开(公告)号：US20080303072A1

公开(公告)日：2008-12-11

申请号：US12178169

申请日：2008-07-23

申请人： Jong-Jan Lee ,  Sheng Teng Hsu ,  Douglas James Tweet ,  Jer-Shen Maa

发明人： Jong-Jan Lee ,  Sheng Teng Hsu ,  Douglas James Tweet ,  Jer-Shen Maa

IPC分类号： H01L31/113

CPC分类号： H01L27/14647

摘要： A CMOS active pixel sensor includes a silicon-on-insulator substrate having a silicon substrate with an insulator layer formed thereon and a top silicon layer formed on the insulator layer. A stacked pixel sensor cell includes a bottom photodiode fabricated on the silicon substrate, for sensing light of a longest wavelength; a middle photodiode fabricated on the silicon substrate, for sensing light of a medium wavelength, which is stacked above the bottom photodiode; and a top photodiode fabricated on the top silicon layer, for sensing light of a shorter wavelength, which is stacked above the middle and bottom photodiodes. Pixel transistor sets are fabricated on the top silicon layer and are associated with each pixel sensor cell by electrical connections which extend between each of the photodiodes and respective pixel transistor(s). CMOS control circuitry is fabricated adjacent to an array of active pixel sensor cells and electrically connected thereto.

摘要翻译： CMOS有源像素传感器包括具有在其上形成有绝缘体层的硅衬底和形成在绝缘体层上的顶部硅层的绝缘体上硅衬底。 层叠像素传感器单元包括：制造在硅衬底上的底部光电二极管，用于感测最长波长的光; 制造在硅衬底上的中间光电二极管，用于感测中等波长的光; 和制造在顶部硅层上的顶部光电二极管，用于感测较短波长的光，该光被层叠在中间和底部光电二极管的上方。 像素晶体管组被制造在顶部硅层上，并且通过在每个光电二极管和相应的像素晶体管之间延伸的电连接与每个像素传感器单元相关联。 CMOS控制电路与有源像素传感器单元的阵列相邻并且与其电连接。

公开(公告)号：US06852652B1

公开(公告)日：2005-02-08

申请号：US10674369

申请日：2003-09-29

申请人： Jer-Shen Maa ,  Jong-Jan Lee ,  Douglas J. Tweet ,  Steve Roy Droes

发明人： Jer-Shen Maa ,  Jong-Jan Lee ,  Douglas J. Tweet ,  Steve Roy Droes

IPC分类号： C23C14/48 ,  H01L21/00 ,  H01L21/02 ,  H01L21/20 ,  H01L21/336 ,  H01L21/762 ,  H01L27/12 ,  H01L29/786

CPC分类号： H01L21/76254 ,  Y10S438/933

摘要： A method of forming a silicon-germanium layer on an insulator includes preparing a silicon substrate; depositing a layer of silicon-germanium on the silicon substrate to form a silicon/silicon-germanium portion; implanting hydrogen ions in the silicon-germanium layer; preparing an insulator substrate; bonding the silicon/silicon-germanium portion to the insulator substrate with the silicon-germanium layer in contact with the insulator substrate to form a bonded entity; curing the bonded entity; and thermally annealing the bonded entity to split the bonded entity into a silicon/silicon germanium portion and a silicon-germanium-on-insulator portion and to relax the silicon germanium layers.

摘要翻译： 在绝缘体上形成硅 - 锗层的方法包括制备硅衬底; 在硅衬底上沉积一层硅 - 锗以形成硅/硅 - 锗部分; 在硅 - 锗层中注入氢离子; 制备绝缘体基板; 将硅/锗锗部分接合到绝缘体衬底，硅 - 锗层与绝缘体衬底接触以形成键合实体; 养护保税实体; 以及对所述结合的实体进行热退火以将所述结合的实体分裂成硅/硅锗部分和绝缘体上的硅 - 锗部分并使所述硅锗层松弛。

公开(公告)号：US07800148B2

公开(公告)日：2010-09-21

申请号：US12178169

申请日：2008-07-23

申请人： Jong-Jan Lee ,  Sheng Teng Hsu ,  Douglas James Tweet ,  Jer-Shen Maa

发明人： Jong-Jan Lee ,  Sheng Teng Hsu ,  Douglas James Tweet ,  Jer-Shen Maa

IPC分类号： H01L31/062

CPC分类号： H01L27/14647

摘要： A CMOS active pixel sensor includes a silicon-on-insulator substrate having a silicon substrate with an insulator layer formed thereon and a top silicon layer formed on the insulator layer. A stacked pixel sensor cell includes a bottom photodiode fabricated on the silicon substrate, for sensing light of a longest wavelength; a middle photodiode fabricated on the silicon substrate, for sensing light of a medium wavelength, which is stacked above the bottom photodiode; and a top photodiode fabricated on the top silicon layer, for sensing light of a shorter wavelength, which is stacked above the middle and bottom photodiodes. Pixel transistor sets are fabricated on the top silicon layer and are associated with each pixel sensor cell by electrical connections which extend between each of the photodiodes and respective pixel transistor(s). CMOS control circuitry is fabricated adjacent to an array of active pixel sensor cells and electrically connected thereto.

摘要翻译： CMOS有源像素传感器包括具有在其上形成有绝缘体层的硅衬底和形成在绝缘体层上的顶部硅层的绝缘体上硅衬底。 层叠像素传感器单元包括：制造在硅衬底上的底部光电二极管，用于感测最长波长的光; 制造在硅衬底上的中间光电二极管，用于感测中等波长的光; 和制造在顶部硅层上的顶部光电二极管，用于感测较短波长的光，该光被层叠在中间和底部光电二极管的上方。 像素晶体管组被制造在顶部硅层上，并且通过在每个光电二极管和相应的像素晶体管之间延伸的电连接与每个像素传感器单元相关联。 CMOS控制电路与有源像素传感器单元的阵列相邻并且与其电连接。

公开(公告)号：US20080164577A1

公开(公告)日：2008-07-10

申请号：US11649634

申请日：2007-01-04

申请人： Tingkai Li ,  Jong-Jan Lee ,  Jer-Shen Maa ,  Sheng Teng Hsu

发明人： Tingkai Li ,  Jong-Jan Lee ,  Jer-Shen Maa ,  Sheng Teng Hsu

IPC分类号： H01L21/3065 ,  H01L29/06

CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L21/306 ,  H01L29/0669 ,  H01L29/0673 ,  Y10S977/743

摘要： An array of submicron silicon (Si) tubes is provided with a method for patterning submicron Si tubes. The method provides a Si substrate, and forms a silicon dioxide film overlying the Si substrate. An array of silicon dioxide rods is formed from the silicon dioxide film, and Si3N4 tubes are formed surrounding the silicon dioxide rods. The silicon dioxide rods are etched away. Then, exposed regions of the Si substrate are etched, forming Si tubes underlying the Si3N4 tubes. Finally, the Si3N4 tubes are removed.

摘要翻译： 亚微米硅（Si）管的阵列具有用于构图亚微米Si管的方法。 该方法提供Si衬底，并形成覆盖Si衬底的二氧化硅膜。 由二氧化硅膜形成二氧化硅棒的阵列，并且在二氧化硅棒周围形成Si 3 N 4 N 4管。 二氧化硅棒被蚀刻掉。 然后，蚀刻Si衬底的暴露区域，形成Si 3 N 4 N 4管子下面的Si管。 最后，去除Si 3 N 4 N 4管。

公开(公告)号：US07405098B2

公开(公告)日：2008-07-29

申请号：US11339017

申请日：2006-01-25

申请人： Jong-Jan Lee ,  Jer-Shen Maa ,  Douglas J. Tweet ,  David R. Evans ,  Allen Burmaster

发明人： Jong-Jan Lee ,  Jer-Shen Maa ,  Douglas J. Tweet ,  David R. Evans ,  Allen Burmaster

IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L21/331 ,  H01L21/76 ,  H01L21/20 ,  H01L21/36

CPC分类号： C30B19/00 ,  C30B29/08 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02623 ,  H01L21/02639 ,  H01L21/30625 ,  H01L21/7624 ,  H01L27/14683 ,  H01L27/14689 ,  H01L29/16 ,  H01L29/78 ,  H01L31/028 ,  H01L31/105 ,  H01L31/1126 ,  H01L31/1136 ,  H01L31/1804 ,  H01L31/1808 ,  Y02E10/547 ,  Y02P70/521

摘要： A method is provided for forming a liquid phase epitaxial (LPE) germanium (Ge)-on-insulator (GOI) thin-film with a smooth surface. The method provides a silicon (Si) wafer, forms a silicon nitride insulator layer overlying the Si wafer, and selectively etches the silicon nitride insulator layer, forming a Si seed access region. Then, the method conformally deposits Ge overlying the silicon nitride insulator layer and Si seed access region, forming a Ge layer with a first surface roughness, and smoothes the Ge layer using a chemical-mechanical polish (CMP) process. Typically, the method encapsulates the Ge layer and anneals the Ge layer to form a LPE Ge layer. A Ge layer is formed with a second surface roughness, less than the first surface roughness. In some aspects, the method forms an active device in the LPE Ge layer.

摘要翻译： 提供一种形成具有光滑表面的液相外延（LPE）锗（Ge） - 绝缘体（GOI）薄膜的方法。 该方法提供硅（Si）晶片，形成覆盖Si晶片的氮化硅绝缘体层，并且选择性地蚀刻氮化硅绝缘体层，形成Si种子接入区域。 然后，该方法共同沉积覆盖氮化硅绝缘体层和Si种子访问区域的Ge，形成具有第一表面粗糙度的Ge层，并且使用化学机械抛光（CMP）工艺平滑Ge层。 通常，该方法封装Ge层并退火Ge层以形成LPE Ge层。 Ge层形成有小于第一表面粗糙度的第二表面粗糙度。 在某些方面，该方法在LPE Ge层中形成有源器件。