Digital signal processor having reconfigurable data paths
    51.
    发明申请
    Digital signal processor having reconfigurable data paths 审中-公开
    具有可重构数据路径的数字信号处理器

    公开(公告)号:US20060271610A1

    公开(公告)日:2006-11-30

    申请号:US11192006

    申请日:2005-07-29

    IPC分类号: G06F15/00

    CPC分类号: G06F7/57

    摘要: Disclosed herein is a Digital Signal Processor (DSP) having reconfigurable data paths necessary for processing for a specific use. The DSP includes a plurality of Arithmetic Logic Units (ALUs), pairs of input multiplexers, an output multiplexer, and a reconfiguration control unit. The plurality of ALUs performs unit operations. Each of the pairs of input multiplexers selects data, which will be input to a corresponding ALU, from among input data directed to operate by an instruction word, and output data of the ALUs. The output multiplexer selects one from among the output data of the ALUs, and outputs the selected output data. The reconfiguration control unit controls the data selections of the output multiplexer and the input multiplexers.

    摘要翻译: 这里公开了具有用于特定用途的处理所需的可重新配置数据路径的数字信号处理器(DSP)。 DSP包括多个算术逻辑单元(ALU),输入多路复用器对,输出多路复用器和重配置控制单元。 多个ALU执行单元操作。 输入多路复用器对中的每一对从选择指令字操作的输入数据和ALU的输出数据中选择将被输入到对应的ALU的数据。 输出多路复用器从ALU的输出数据中选择一个,并输出所选择的输出数据。 重新配置控制单元控制输出多路复用器和输入多路复用器的数据选择。

    Variable capacity rotary compressor

    公开(公告)号:US20060222543A1

    公开(公告)日:2006-10-05

    申请号:US11246251

    申请日:2005-10-11

    IPC分类号: F03C2/00 F01C1/02 F04C18/00

    摘要: A variable capacity rotary compressor to securely fix a clutch pin to a rotation shaft includes first and second compression chambers having different inner volumes, a rotation shaft penetrating the first and second compression chambers, first and second eccentric bushes disposed on an outer circumference of the rotation shaft, a slot provided between the first and second eccentric bushes, a clutch pin protruding from the rotation shaft and disposed in the slot, and a fixing pin coupled with the side of the clutch pin in the rotation shaft to securely fix the clutch pin to the rotation shaft. A groove having a predetermined width can be formed at a rear side of the clutch pin and a rear side of the fixing pin can be inserted into the groove to couple with the clutch pin in the rotation shaft.

    LED package frame and LED package having the same
    55.
    发明申请
    LED package frame and LED package having the same 有权
    LED封装框架和LED封装相同

    公开(公告)号:US20060169999A1

    公开(公告)日:2006-08-03

    申请号:US11319101

    申请日:2005-12-28

    IPC分类号: H01L33/00

    摘要: The invention relates to an LED package frame and an LED package incorporating the same. The LED package frame comprises an LED chip; and a heat conductive member made of a lump of high heat conductivity material. The heat conductive member has a receiving part at a lateral portion, and is mounted with the LED chip. A lead is inserted at one end into the receiving part of the heat conductive member, and electrically connected to the LED chip. An electrically insulating layer is placed in tight contact between the lead and the receiving part of the heat conductive member to separate the lead from the receiving part. With the lead inserted into the heat conductive member, it is possible to reduce size while maintaining high heat conductivity and stability. Also, it is possible to provide an LED package frame and a high power LED package by fixing the lead fixed to the heat conductive member without a jig.

    摘要翻译: 本发明涉及一种LED封装框架和一个包含该LED封装框架的LED封装件。 LED封装框架包括LED芯片; 以及由高导热性材料块制成的导热构件。 导热构件在侧部具有接收部,并且安装有LED芯片。 引线一端插入导热部件的接收部分,并与LED芯片电连接。 电绝缘层被放置在引导件和导热构件的接收部分之间的紧密接触中以将引线与接收部分分离。 通过将导线插入导热构件,可以在保持高导热性和稳定性的同时减小尺寸。 此外,通过将固定在导热构件上的引线固定而不用夹具,可以提供LED封装框架和大功率LED封装。

    Method of manufacturing flash memory device
    56.
    发明申请
    Method of manufacturing flash memory device 审中-公开
    制造闪存设备的方法

    公开(公告)号:US20060141725A1

    公开(公告)日:2006-06-29

    申请号:US11129776

    申请日:2005-05-16

    申请人: Seung Lee Sang Park

    发明人: Seung Lee Sang Park

    IPC分类号: H01L21/336

    摘要: A method of manufacturing a flash memory device wherein before an insulating film spacer of a contact region is removed after a gate line and source/drain are formed, a high quality buffer oxide film formed between the gate line and the insulating film spacer is made dense by means of an annealing process. Abnormal oxidization is thus prevented from occurring due to an exposed metal layer in a gate when the insulating film spacer is removed as at least part of the buffer oxide remains after the spacer is removed.

    摘要翻译: 一种制造闪存器件的方法,其中在形成栅极线和源极/漏极之后去除接触区域的绝缘膜间隔物之前,形成在栅极线和绝缘膜间隔物之间​​的高质量缓冲氧化膜被制成密集 通过退火工艺。 因此,当绝缘膜间隔物被去除时,防止在栅极中暴露的金属层发生异常氧化,因为至少部分缓冲氧化物在除去间隔物后残留。

    Current cell and digital-to-analog converter using the same
    58.
    发明申请
    Current cell and digital-to-analog converter using the same 审中-公开
    当前单元和数模转换器使用相同

    公开(公告)号:US20060125670A1

    公开(公告)日:2006-06-15

    申请号:US11253181

    申请日:2005-10-18

    IPC分类号: H03M1/66

    摘要: Provided are a current cell and digital-to-analog converter (DAC) using the same. The current cell includes a current source; a first transistor transmitting a current produced from the current source to a first output node based on a first signal; a second transistor transmitting a current produced from the current source to a second output node based on a second signal; a first capacitor coupled between a gate of the first transistor and the second output node; and a second capacitor coupled between a gate of the second transistor and the first output node. A current mode DAC can improve in dynamic performance by using a plurality of current cells each having the above-described configuration.

    摘要翻译: 提供了使用其的当前单元和数模转换器(DAC)。 当前单元包括电流源; 第一晶体管,基于第一信号将从电流源产生的电流传输到第一输出节点; 基于第二信号将从电流源产生的电流传输到第二输出节点的第二晶体管; 耦合在所述第一晶体管的栅极和所述第二输出节点之间的第一电容器; 以及耦合在所述第二晶体管的栅极和所述第一输出节点之间的第二电容器。 电流模式DAC可以通过使用具有上述配置的多个当前单元来改善动态性能。

    Method of fabricating SiGe Bi-CMOS device
    59.
    发明申请
    Method of fabricating SiGe Bi-CMOS device 失效
    制造SiGe Bi-CMOS器件的方法

    公开(公告)号:US20060121667A1

    公开(公告)日:2006-06-08

    申请号:US11283012

    申请日:2005-11-18

    IPC分类号: H01L21/8238

    CPC分类号: H01L21/8249

    摘要: Provided is a method of fabricating a silicon germanium (SiGe) Bi-CMOS device. In the fabrication method, the source and drain of the CMOS device is formed using a silicon germanium (SiGe) heterojunction, instead of silicon, thereby preventing a leakage current resulting from a parasitic bipolar operation. Further, since the source and drain is connected with an external interconnection through the nickel (Ni) silicide layer, the contact resistance is reduced, thereby preventing loss of a necessary voltage for a device operation and accordingly, making it possible to enable a low voltage and low power operation and securing a broad operation region even in a low voltage operation of an analogue circuit.

    摘要翻译: 提供一种制造硅锗(SiGe)Bi-CMOS器件的方法。 在制造方法中,使用硅锗(SiGe)异质结代替硅形成CMOS器件的源极和漏极,从而防止由寄生双极性操作引起的漏电流。 此外,由于源极和漏极通过镍(Ni)硅化物层与外部互连件连接,所以接触电阻降低,从而防止器件操作所需的电压的损失,并因此使得能够实现低电压 并且即使在模拟电路的低电压操作下也能实现低功率操作并确保宽的操作区域。

    Method for forming wall oxide layer and isolation layer in flash memory device
    60.
    发明申请
    Method for forming wall oxide layer and isolation layer in flash memory device 失效
    在闪速存储器件中形成壁氧化物层和隔离层的方法

    公开(公告)号:US20060073661A1

    公开(公告)日:2006-04-06

    申请号:US11016436

    申请日:2004-12-17

    申请人: Seung Lee

    发明人: Seung Lee

    IPC分类号: H01L21/76

    摘要: Disclosed herein are methods for forming wall oxide films in flash memory devices and methods for forming isolation films. After trenches are formed in the substrate, an ISSG (In-Situ Steam Generation) oxidization process is performed to form wall oxide films on sidewalls of the trenches. This process prohibits formation of facets at the top and bottom edge portions of the trenches. Thus, the top edges of the trenches are rounded. Furthermore, the ISSG oxidization process is performed at a low temperature for a relatively short time. Therefore, thermal stress due to carrying out an oxidization process for a long time is reduced and a dislocation phenomenon is thus prevented from occurring.

    摘要翻译: 本文公开了在快闪存储器件中形成壁氧化膜的方法和用于形成隔离膜的方法。 在衬底中形成沟槽之后,进行ISSG(原位蒸汽生成)氧化处理以在沟槽的侧壁上形成壁氧化物膜。 该过程禁止在沟槽的顶部和底部边缘部分形成小面。 因此,沟槽的顶部边缘是圆形的。 此外,ISSG氧化过程在较短的时间内在低温下进行。 因此,长时间进行氧化处理引起的热应力降低,从而防止发生位错现象。