公开(公告)号：US06839806B2

公开(公告)日：2005-01-04

申请号：US09941696

申请日：2001-08-30

申请人： Yoshiki Murakami ,  Masaru Koyanagi ,  Hideya Akashi

发明人： Yoshiki Murakami ,  Masaru Koyanagi ,  Hideya Akashi

IPC分类号： G06F12/08 ,  G06F12/12 ,  G06F12/00

CPC分类号： G06F12/0855 ,  G06F12/0831

摘要： A cache system comprising a cache tag buffer 270 for storing a part of a cache tag memory 260. When a memory processing request is issued from a processor 10, a cache control means 280 retrieves both of the cache tag memory 260 and the cache tag buffer 270. If a target cache block is present in the cache tag buffer 270, then, without waiting for a retrieval result of the cache tag memory 260, the cache control circuit 280 accesses the cache data memory 250 using information of the cache block.

公开(公告)号：US06762968B2

公开(公告)日：2004-07-13

申请号：US10322405

申请日：2002-12-17

申请人： Yashiro Suematsu ,  Masaru Koyanagi

发明人： Yashiro Suematsu ,  Masaru Koyanagi

IPC分类号： G11C700

CPC分类号： G11C7/12 ,  G11C11/4074 ,  G11C11/4094

摘要： The bit line overdrive circuit of the present invention comprises a VBLH potential generation circuit generating a bit line final potential relative to a VBLH power supply line for driving a sense amplifier, a charge adjusting capacitance C, a transistor for supplying an overdrive potential to the VBLH power supply line, and a transistor for connecting a PCS node to the VBLH power supply line. The charge pre-charged from the overdrive potential to the VBLH power supply line is shared among the capacitance of the above-noted circuit elements connected to the VBLH power supply line, the bit line capacitance, and the capacitance of a cell capacitor so as to form a VBLH power supply of a substantially one system, thereby avoiding the generation of a power supply noise caused by the power supply switching.

摘要翻译： 本发明的位线过驱动电路包括VBLH电位产生电路，其相对于用于驱动读出放大器的VBLH电源线产生位线最终电位，电荷调整电容C，用于向VBLH提供过驱动电位的晶体管 电源线和用于将PCS节点连接到VBLH电源线的晶体管。 从过驱动电位预充电到VBLH电源线的电荷在连接到VBLH电源线的上述电路元件的电容，位线电容和单元电容器的电容之间共享，以便 形成基本上一个系统的VBLH电源，从而避免由电源切换引起的电源噪声的产生。

公开(公告)号：US06665226B2

公开(公告)日：2003-12-16

申请号：US10272243

申请日：2002-10-15

申请人： Kazuhide Yoneya ,  Masaru Koyanagi

发明人： Kazuhide Yoneya ,  Masaru Koyanagi

IPC分类号： G11C700

CPC分类号： G11C17/18 ,  G11C7/1045 ,  G11C17/16 ,  G11C29/023 ,  G11C29/028

摘要： A semiconductor integrated circuit device including an integrated circuit portion, a fuse element block, and a data transfer selecting circuit. The fuse element block includes a programmable fuse element. The data transfer selecting circuit selects one of the transfer of data programmed in the fuse element to the integrated circuit portion, transfer of data input from outside to the integrated circuit portion, and transfer of data programmed in the fuse element to outside.

摘要翻译： 一种包括集成电路部分，熔丝元件块和数据传输选择电路的半导体集成电路器件。 熔丝元件块包括可编程熔丝元件。 数据传输选择电路选择在熔丝元件中编程的数据到集成电路部分的传送，从外部输入到集成电路部分的数据传送，以及将在熔丝元件中编程的数据传送到外部。

公开(公告)号：US06657531B2

公开(公告)日：2003-12-02

申请号：US10026230

申请日：2001-12-21

申请人： Tohru Kimura ,  Masaru Koyanagi

发明人： Tohru Kimura ,  Masaru Koyanagi

IPC分类号： H01H8530

CPC分类号： G11C17/18 ,  H01L2924/0002 ,  H01L2924/00

摘要： A fuse circuit includes electrical fuse elements which are commonly connected at one-side ends, a voltage generating section and a readout section. The voltage generating section is configured to selectively apply program voltage for destroying the electrical fuse element and read voltage for reading out the destructive/nondestructive states of the electrical fuse elements to a common connection node of the one-side ends of the electrical fuse elements. The readout section is configured to read out the destructive/nondestructive states of the electrical fuse elements from the other ends of the electrical fuse elements when the read voltage is applied to the common connection node from the voltage generating section.

公开(公告)号：US06466490B2

公开(公告)日：2002-10-15

申请号：US09956255

申请日：2001-09-20

申请人： Takeshi Nagai ,  Takahiko Hara ,  Masaru Koyanagi

发明人： Takeshi Nagai ,  Takahiko Hara ,  Masaru Koyanagi

IPC分类号： G11C700

CPC分类号： G11C29/38 ,  G11C29/88 ,  G11C2029/2602

摘要： A semiconductor memory circuit capable of conducting an efficient test by using a memory tester is provided. A semiconductor memory circuit includes a memory cell array; a plurality of main data lines for conducting reading and writing every plural bits in parallel; and a shift register for converting parallel data read from memory cell array to the main data lines into serial data and supplying the converted data to data input/output terminals, and for converting write data supplied from the data input/output terminals in series into parallel data and supplying the converted data to the main data lines, and at least a portion of a plurality of the main data lines are arranged so as to be across each other between the memory cell array and the shift register. As a result, data compression is enabled during a test by a memory tester.

摘要翻译： 提供了能够通过使用存储器测试器进行有效测试的半导体存储器电路。 半导体存储器电路包括存储单元阵列; 多条主数据线，用于并行地进行读取和写入; 以及用于将从存储单元阵列读取的并行数据转换为主数据线的移位寄存器，作为串行数据，并将转换的数据提供给数据输入/输出端，并将从数据输入/输出端子提供的写入数据串行转换为并行 数据并将转换的数据提供给主数据线，并且多个主数据线的至少一部分被布置成在存储单元阵列和移位寄存器之间彼此相对。 因此，在内存测试仪的测试期间启用数据压缩。

公开(公告)号：US06370077B1

公开(公告)日：2002-04-09

申请号：US09545438

申请日：2000-04-07

申请人： Masaru Koyanagi ,  Kaoru Nakagawa ,  Takahiko Hara ,  Satoru Takase

发明人： Masaru Koyanagi ,  Kaoru Nakagawa ,  Takahiko Hara ,  Satoru Takase

IPC分类号： G11C800

CPC分类号： G11C8/18 ,  G11C8/12 ,  G11C11/406

摘要： A DRAM, including a plurality of banks each having a plurality of sub-arrays, and sense amplifier circuits commonly shared by sub-arrays in different banks, has a row access mode for activating a sub-array selected from each bank for reading or writing data, and a refresh mode for activating a plurality of sub-arrays in each bank and refreshing memory cell data therein at substantially the same timing. Sub-arrays in each bank activated at substantially the same timing in the refresh mode are more than sub-arrays in each bank activated in the row access model. Thereby, occurrence of operation constrains is minimized to ensure high-speed operation and improve the system performance of DRAMs employing the non-independent bank system.

公开(公告)号：US06349069B2

公开(公告)日：2002-02-19

申请号：US09879145

申请日：2001-06-13

申请人： Kenichi Matoba ,  Masaru Koyanagi

发明人： Kenichi Matoba ,  Masaru Koyanagi

IPC分类号： G11C800

CPC分类号： G11C8/12

摘要： A semiconductor memory device comprises a first core section including a plurality of memory cell arrays, a second core section including a plurality of memory cell arrays and provided below the first core section, a third core section including a plurality of memory cell arrays and provided in a right side of the first core section, and a fourth core section including a plurality of memory cell arrays and provided in a right side of the second core section, wherein at least a part of the memory cell arrays of the first core section and at least a part of the memory cell arrays of the fourth core section are simultaneously activated, and at least a part, of the memory cell arrays of the second core section and at least a part of the memory cell arrays of the third core section are simultaneously activated.

摘要翻译： 半导体存储器件包括：第一芯部分，包括多个存储单元阵列;第二芯部分，包括多个存储单元阵列并且设置在第一芯部下;第三核心部分，包括多个存储单元阵列， 第一芯部的右侧，以及包括多个存储单元阵列并设置在第二芯部的右侧的第四芯部，其中，第一芯部的存储单元阵列的至少一部分和 同时激活第四核心部分的存储单元阵列的至少一部分，并且第二核心部分的存储单元阵列和第三核心部分的至少一部分存储单元阵列的至少一部分同时 活性。

公开(公告)号：US5955891A

公开(公告)日：1999-09-21

申请号：US572381

申请日：1995-12-14

申请人： Eiichi Makino ,  Masaru Koyanagi

发明人： Eiichi Makino ,  Masaru Koyanagi

IPC分类号： G05F1/56 ,  G05F3/24 ,  G11C11/401 ,  G11C11/407 ,  G11C11/409 ,  H03K19/00 ,  H03K19/003 ,  H03K19/0185

CPC分类号： H03K19/00361

摘要： The control voltage .phi.1 outputted by the control voltage generating circuit 1 is at a low level in a range where an external supply voltage Vcc is lower than the threshold value of the transistor P1, but increases continuously in analog manner when the external supply voltage Vcc rises. After having matched the external supply voltage Vcc, the control voltage .phi.1 increases in the same way as the external supply voltage Vcc. By use of the control voltage provided with the characteristics as described above for an output circuit, controlled is the gate of a transistor P4 of a low-voltage operating output section 6 operative only at a voltage lower than a predetermined value. The transistor P2 of a full-voltage operating output section 5 of the output circuit is always operative on the basis of the control signal .phi.H of the data output control circuit 3. When the external supply voltage is low below the predetermined value, the transistor P4 is perfectly turned on, so that the conductance thereof increases. In the semiconductor integrated circuit device operative on the basis of a plurality of supply voltages, it is possible to prevent the operation margin from being reduced near the switching point of the gate voltages of the driving transistors and the data output transistors.

摘要翻译： 控制电压产生电路1输出的控制电压phi 1在外部电源电压Vcc低于晶体管P1的阈值的范围内处于低电平，但是当外部电源电压Vcc 上升。 在匹配外部电源电压Vcc之后，控制电压phi 1以与外部电源电压Vcc相同的方式增加。 通过使用具有如上所述的用于输出电路的特性的控制电压，受控的是低电压工作输出部分6的晶体管P4的栅极仅在低于预定值的电压下工作。 输出电路的全压工作输出部分5的晶体管P2总是基于数据输出控制电路3的控制信号phi H而工作。当外部电源电压低于预定值时，晶体管 P4完全打开，使其电导增加。 在基于多个电源电压工作的半导体集成电路装置中，可以防止在驱动晶体管和数据输出晶体管的栅极电压的切换点附近的操作余量减小。

公开(公告)号：US5347145A

公开(公告)日：1994-09-13

申请号：US813524

申请日：1991-12-26

申请人： Hiroaki Tanaka ,  Masaru Koyanagi

发明人： Hiroaki Tanaka ,  Masaru Koyanagi

IPC分类号： G01R31/26 ,  G01R31/28 ,  G01R31/30 ,  G01R31/3161 ,  H01L21/66 ,  H01L23/485 ,  H01L23/58 ,  H01L23/02

CPC分类号： H01L24/06 ,  G01R31/2884 ,  G01R31/30 ,  G01R31/3161 ,  H01L22/32 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/14

摘要： A semiconductor device comprises a rectangular semiconductor chip provided with an integrated circuit, and a plurality of voltage stress examination pads formed on the semiconductor chip for applying stress examination voltage to the integrated circuit, and having the same function, wherein the voltage stress examination pads are provided on opposite sides of the semiconductor chip.

摘要翻译： 一种半导体器件，包括设置有集成电路的矩形半导体芯片和形成在半导体芯片上的用于向集成电路施加应力检测电压并具有相同功能的多个电压应力检查焊盘，其中电压应力检查焊盘为 设置在半导体芯片的相对侧。

公开(公告)号：US5341013A

公开(公告)日：1994-08-23

申请号：US905661

申请日：1992-06-29

申请人： Masaru Koyanagi ,  Minoru Yamda

发明人： Masaru Koyanagi ,  Minoru Yamda

IPC分类号： G11C11/419 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/10 ,  H01L27/108 ,  H01L27/02

CPC分类号： H01L27/088

摘要： A semiconductor device provided with a plurality of sense circuits, each sense circuit including a pair of MOS transistors such that their sources are commonly connected, and that the drain of one transistor and the gate of the other transistor are cross-coupled each other to, thus, sense a difference between potentials applied to the respective gates. The paired transistors respectively include one transistor regions, and are disposed with their source regions being shared among the plurality of sense circuits. These sense circuits are disposed in a manner to share the source regions of the respective transistors. When elimination of only isolation between sense circuits meets with a required miniaturization of the device, paired transistors constituting sense circuits may include two transistor regions or more connected in parallel, respectively.

摘要翻译： 一种设置有多个感测电路的半导体器件，每个感测电路包括一对MOS晶体管，使得它们的源极共同连接，并且一个晶体管的漏极和另一个晶体管的栅极彼此交叉耦合， 因此，感测施加到各个门的电位之间的差异。 成对晶体管分别包括一个晶体管区域，并且被布置成它们的源极区域在多个感测电路之间共享。 这些感测电路以共享各个晶体管的源极区域的方式设置。 当消除感测电路之间的仅隔离器件满足设备所需的小型化时，构成感测电路的成对晶体管可以分别包括两个或多个并联连接的晶体管区域。