公开(公告)号：US06596615B2

公开(公告)日：2003-07-22

申请号：US09481385

申请日：2000-01-12

申请人： Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Yasuo Yamaguchi

发明人： Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Yasuo Yamaguchi

IPC分类号： H01L218238

CPC分类号： H01L29/66772 ,  H01L21/76224 ,  H01L21/76264 ,  H01L21/76281 ,  H01L29/0638 ,  H01L29/78609

摘要： A sidewall oxide layer and a sidewall insulation layer are formed to cover the edge portion of an SOI layer. A channel stopper region is formed in the vicinity of the edge portion of the SOI layer. A protruded insulation layer is formed on the channel stopper region. A gate electrode extends from a region over the SOI layer to the protruded insulation layer and the sidewall insulation layer. In this way, reduction in threshold voltage Vth of a parasitic MOS transistor at the edge portion of the SOI layer can be suppressed.

公开(公告)号：US06495898B1

公开(公告)日：2002-12-17

申请号：US09639953

申请日：2000-08-17

申请人： Toshiaki Iwamatsu ,  Takashi Ipposhi ,  Takuji Matsumoto

发明人： Toshiaki Iwamatsu ,  Takashi Ipposhi ,  Takuji Matsumoto

IPC分类号： H01L2900

CPC分类号： H01L21/84 ,  H01L21/76264 ,  H01L21/76281 ,  H01L21/76283 ,  H01L27/1203

摘要： In a combined isolation oxide film (BT1), a part closer to a gate electrode (GT13) reaches a buried oxide film (2) through an SOI layer (3) while a part closer to another gate electrode (GT12) has a sectional shape provided with a well region on its lower portion. The shape of an edge portion of the combined isolation oxide film (BT1) is in the form of a bird's beak in a LOCOS isolation oxide film. Consequently, the thicknesses of portions defining edge portions of the gate oxide films (GO12, GO13) are locally increased. Thus provided are a semiconductor device including a MOS transistor having a gate oxide film prevented from dielectric breakdown without increasing its thickness and a method of manufacturing the same.

摘要翻译： 在组合隔离氧化膜（BT1）中，靠近栅电极（GT13）的部分通过SOI层（3）到达埋入氧化膜（2），而靠近另一栅电极（GT12）的部分具有截面形状 在其下部设置有井区。 组合隔离氧化膜（BT1）的边缘部分的形状在LOCOS隔离氧化膜中呈鸟喙的形式。 因此，限定栅极氧化膜（GO12，GO13）的边缘部分的部分的厚度局部增加。 这样提供了一种半导体器件及其制造方法，该半导体器件包括具有防止绝缘击穿而不增加其厚度的栅极氧化膜的MOS晶体管。

公开(公告)号：US06461935B2

公开(公告)日：2002-10-08

申请号：US09989152

申请日：2001-11-21

申请人： Shoichi Miyamoto ,  Toshiaki Iwamatsu ,  Takashi Ipposhi

发明人： Shoichi Miyamoto ,  Toshiaki Iwamatsu ,  Takashi Ipposhi

IPC分类号： H01L2176

CPC分类号： H01L21/76264 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203

摘要： A semiconductor device having a trench-shaped isolator, adjacent to the semiconductor element region is formed having a width which is continuously decreased in the downward direction for relaxing the stress in the silicon layer. Embodiments include forming a patterned dielectric layer on an SOI substrate, forming sidewall spacers thereon, and etching the underlying silicon layer followed by oxidation or controlled etching to form the trench with downwardly decreasing side surfaces.

摘要翻译： 具有与半导体元件区域相邻的沟槽形隔离器的半导体器件形成为具有在向下方向上连续减小的宽度，以缓解硅层中的应力。 实施例包括在SOI衬底上形成图案化的电介质层，在其上形成侧壁间隔物，并蚀刻下面的硅层，接着进行氧化或受控蚀刻，以形成具有向下减少的侧表面的沟槽。

公开(公告)号：US06372599B1

公开(公告)日：2002-04-16

申请号：US09371027

申请日：1999-08-10

申请人： Shoichi Miyamoto ,  Toshiaki Iwamatsu ,  Takashi Ipposhi

发明人： Shoichi Miyamoto ,  Toshiaki Iwamatsu ,  Takashi Ipposhi

IPC分类号： H01L2176

CPC分类号： H01L21/76264 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203

摘要： The invention provides a semiconductor device having the trench-shaped isolator is provided with a portion which is adjacent to the semiconductor element region, of which the width is continuously decreased in the downward direction, and of which the surface is planarized near the semiconductor element region, for relaxing the stress in the silicon layer and being flat the surface of the trench-shaped insulator, and method of manufacturing the same.

公开(公告)号：US5841171A

公开(公告)日：1998-11-24

申请号：US746951

申请日：1996-11-18

申请人： Toshiaki Iwamatsu ,  Takashi Ipposhi ,  Yasuo Inoue

发明人： Toshiaki Iwamatsu ,  Takashi Ipposhi ,  Yasuo Inoue

IPC分类号： H01L21/316 ,  H01L21/76 ,  H01L21/762 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L29/00

CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/78609 ,  H01L29/78654

摘要： In forming an element isolating region in a silicon semiconductor layer of an SOI substrate, a silicon nitride film of a predetermined thickness is deposited over an oxide film formed on a SOI layer. The silicon nitride film is patterned in a design size of active regions, and side walls of a silicon nitride film are formed on the side surfaces of the patterned silicon nitride film. A first LOCOS process is carried out using the nitride film as an oxidation mask. A LOCOS film formed by the first LOCOS process is removed to form narrower concavities under the side walls. Then, another silicon nitride film is deposited, and is removed leaving portions thereof forming the concavities. Then, a second LOCOS process is carried out to form a LOCOS film as an element isolating region. The second LOCOS process uses the oxidation mask having the narrow cavities, so that stress at the boundary of the active region and the element isolation region is reduced, and the growth of bird's beaks can be suppressed.

摘要翻译： 在形成SOI衬底的硅半导体层中的元件隔离区域时，在形成于SOI层上的氧化物膜上沉积预定厚度的氮化硅膜。 以活性区域的设计尺寸对氮化硅膜进行构图，并且在图案化的氮化硅膜的侧表面上形成氮化硅膜的侧壁。 使用氮化物膜作为氧化掩模进行第一LOCOS工艺。 去除由第一LOCOS工艺形成的LOCOS膜，以在侧壁下形成更窄的凹面。 然后，沉积另一个氮化硅膜，并除去形成凹部的部分。 然后，进行第二LOCOS工艺以形成LOCOS膜作为元件隔离区。 第二LOCOS工艺使用具有窄腔的氧化掩模，使得有源区域和元件隔离区域的边界处的应力减小，并且可以抑制鸟喙的生长。

公开(公告)号：US5061655A

公开(公告)日：1991-10-29

申请号：US653086

申请日：1991-02-11

申请人： Takashi Ipposhi ,  Kozuyuki Sugahara

发明人： Takashi Ipposhi ,  Kozuyuki Sugahara

IPC分类号： H01L21/20 ,  H01L21/263 ,  H01L21/321 ,  H01L21/762

CPC分类号： H01L21/2026 ,  H01L21/321 ,  H01L21/76248 ,  Y10S117/904 ,  Y10S148/093 ,  Y10S148/154

摘要： A method of producing so-called SOI structures according to this invention includes the step of forming an opening for seeding after an insulating layer of predetermined thickness has been formed on a first monocrystal silicon layer. Further, a non-monocrystal layer, e.g., a polycrystal silicon layer is formed on the surface of the insulating layer. The surface of the polycrystal silicon layer is smoothed as by grinding. A reflection-preventive film is formed on the smoothed surface of the polycrystal silicon layer. The reflection-preventive film has a thin film region whose reflectance is substantially zero and a thick film region having a predetermined reflectance. During laser annealing, the reflection-preventive film produces a predetermined temperature distribution in the polycrystal silicon layer. The polycrystal silicon layer which has melted according to this temperature distribution recrystallizes from adjacent the seed portion and thereby forms a new monocrystal silicon layer over the entire surface. The smoothing process for the polycrystal silicon layer prevents any change in the reflectance of the reflection-preventive film and improves control on the temperature distribution in the polycrystal silicon layer.

摘要翻译： 根据本发明的制造所谓的SOI结构的方法包括在第一单晶硅层上形成预定厚度的绝缘层之后形成用于接种​​的开口的步骤。 此外，在绝缘层的表面上形成非单晶层，例如多晶硅层。 多晶硅层的表面通过研磨而平滑化。 在多晶硅层的平滑表面上形成防反射膜。 防反射膜具有反射率基本为零的薄膜区域和具有预定反射率的厚膜区域。 在激光退火期间，防反射膜在多晶硅层中产生预定的温度分布。 根据该温度分布熔融的多晶硅层从种子部分相邻再结晶，从而在整个表面上形成新的单晶硅层。 多晶硅层的平滑处理防止防反射膜的反射率的任何变化，并且改善对多晶硅层中的温度分布的控制。

公开(公告)号：US08067804B2

公开(公告)日：2011-11-29

申请号：US11251911

申请日：2005-10-18

申请人： Shigeto Maegawa ,  Takashi Ipposhi

发明人： Shigeto Maegawa ,  Takashi Ipposhi

IPC分类号： H01L29/786

CPC分类号： H01L29/78621 ,  H01L21/84 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1203 ,  H01L29/78615 ,  H01L29/78624

摘要： The present invention provides a semiconductor device capable of suppressing a body floating effect, and a manufacturing method thereof. A semiconductor device having an SOI structure includes a silicon substrate, a buried insulating layer formed on the silicon substrate, and a semiconductor layer formed on the buried insulating layer. The semiconductor layer has a body region of a first conduction type, a source region of a second conduction type and a drain region of the second conduction type, and a gate electrode is formed on the body region between the source region and the drain region via a gate oxide film. The source region includes an extension layer of the second conduction type, and a silicide layer which makes contact with the extension layer at its side face, and a crystal defect region is formed on a region of a depletion layer generated in a boundary portion between the silicide layer and the body region.

摘要翻译： 本发明提供能够抑制身体浮动效应的半导体器件及其制造方法。 具有SOI结构的半导体器件包括硅衬底，形成在硅衬底上的掩埋绝缘层和形成在掩埋绝缘层上的半导体层。 半导体层具有第一导电类型的主体区域，第二导电类型的源极区域和第二导电类型的漏极区域，并且栅极电极形成在源极区域和漏极区域通孔之间的体区域上 栅氧化膜。 源极区域包括第二导电类型的延伸层和在其侧面与延伸层接触的硅化物层，并且在位于第二导电类型之间的边界部分中产生的耗尽层的区域上形成晶体缺陷区域 硅化物层和身体区域。

公开(公告)号：US07898032B2

公开(公告)日：2011-03-01

申请号：US11672487

申请日：2007-02-07

申请人： Takaya Suzuki ,  Takashi Ipposhi

发明人： Takaya Suzuki ,  Takashi Ipposhi

IPC分类号： H01L27/12

CPC分类号： H01L27/0629 ,  H01L28/20 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention realizes the miniaturization of a semiconductor device. On a first insulation film, an island-like semiconductor layer and a second insulation film which surrounds the semiconductor layer are formed, and resistance elements (for example, poly-silicon resistance elements) which are formed of a conductive film are arranged to be overlapped to an upper surface of the semiconductor layer in plane.

摘要翻译： 本发明实现了半导体器件的小型化。 在第一绝缘膜上形成围绕半导体层的岛状半导体层和第二绝缘膜，并且由导电膜形成的电阻元件（例如，多晶硅电阻元件）被布置成重叠 到半导体层的上表面。

公开(公告)号：US07786534B2

公开(公告)日：2010-08-31

申请号：US12399062

申请日：2009-03-06

申请人： Yukio Maki ,  Takashi Ipposhi ,  Toshiaki Iwamatsu

发明人： Yukio Maki ,  Takashi Ipposhi ,  Toshiaki Iwamatsu

IPC分类号： H01L27/01

CPC分类号： H01L21/84 ,  H01L21/743 ,  H01L23/585 ,  H01L27/1203 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00

摘要： A plurality of conductive layers and a plurality of wiring layers connecting a supporting substrate having SOI structure and uppermost wire are formed along a peripheral part of a semiconductor chip together with the uppermost wire, to thereby surround a transistor forming region in which a transistor is to be formed.

摘要翻译： 沿着半导体芯片的周边部分与最上面的导线一起形成多个导电层和连接具有SOI结构的支撑衬底和最上面的线的多个布线层，从而围绕晶体管形成区域 形成。

公开(公告)号：US07675122B2

公开(公告)日：2010-03-09

申请号：US11889704

申请日：2007-08-15

申请人： Yuuichi Hirano ,  Takashi Ipposhi ,  Shigeto Maegawa ,  Koji Nii

发明人： Yuuichi Hirano ,  Takashi Ipposhi ,  Shigeto Maegawa ,  Koji Nii

IPC分类号： H01L29/76 ,  H01L29/94

CPC分类号： H01L21/84 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1203 ,  Y10S257/903 ,  Y10S257/904

摘要： A contact connected to a word line is formed on a gate electrode of an access transistor of an SRAM cell. The contact passes through an element isolation insulating film to reach an SOI layer. A body region of a driver transistor and that of the access transistor are electrically connected with each other through the SOI layer located under the element isolation insulating film. Therefore, the access transistor is in a DTMOS structure having the gate electrode connected with the body region through the contact, which in turn is also electrically connected to the body region of the driver transistor. Thus, operations can be stabilized while suppressing increase of an area for forming the SRAM cell.

摘要翻译： 连接到字线的触点形成在SRAM单元的存取晶体管的栅电极上。 接触通过元件隔离绝缘膜以达到SOI层。 驱动晶体管的体区和存取晶体管的体区通过位于元件隔离绝缘膜下方的SOI层彼此电连接。 因此，存取晶体管是具有通过触点与主体区域连接的栅电极的DTMOS结构，该触点又电连接到驱动晶体管的体区。 因此，可以在抑制用于形成SRAM单元的区域的增加的同时稳定操作。