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    CROSS-POINT MEMORY AND METHODS FOR FABRICATION OF SAME
    51.
    发明申请
    CROSS-POINT MEMORY AND METHODS FOR FABRICATION OF SAME 审中-公开

    公开(公告)号：US20170365642A1

    公开(公告)日：2017-12-21

    申请号：US15693102

    申请日：2017-08-31

    Applicant: Micron Technology, Inc.

    Inventor： Marcello Ravasio ,  Samuele Sciarrillo ,  Fabio Pellizzer ,  Innocenzo Tortorelli ,  Roberto Somaschini ,  Cristina Casellato ,  Riccardo Mottadelli

    IPC: H01L27/24 ,  H01L45/00

    CPC classification number: H01L27/2463 ,  H01L27/2427 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1675

    Abstract: The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a method of fabricating cross-point memory arrays comprises forming a memory cell material stack which includes a first active material and a second active material over the first active material, wherein one of the first and second active materials comprises a storage material and the other of the first and second active materials comprises a selector material. The method of fabricating cross-point arrays further comprises patterning the memory cell material stack, which includes etching through at least one of the first and second active materials of the memory cell material stack, forming protective liners on sidewalls of the at least one of the first and second active materials after etching through the one of the first and second active materials, and further etching the memory cell material stack after forming the protective liners on the sidewalls of the one of the first and second active materials.

    APPARATUSES AND METHODS OF READING MEMORY CELLS BASED ON RESPONSE TO A TEST PULSE
    53.
    发明申请
    APPARATUSES AND METHODS OF READING MEMORY CELLS BASED ON RESPONSE TO A TEST PULSE 审中-公开

    公开(公告)号：US20170309331A1

    公开(公告)日：2017-10-26

    申请号：US15588301

    申请日：2017-05-05

    Applicant: Micron Technology, Inc.

    Inventor： Innocenzo Tortorelli ,  Fabio Pellizzer

    IPC: G11C13/00 ,  G11C11/56

    CPC classification number: G11C13/004 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2013/0045 ,  G11C2013/0057

    Abstract: The disclosed technology generally relates to memory apparatuses and methods of operating the same, and more particularly to memory arrays and methods of reading memory cells in a memory array, such as a cross point memory array. In one aspect, the method comprises providing a memory array comprising a memory cell in one of a plurality of states. The method additionally comprises determining whether a threshold voltage (Vth) of the memory cell has a value within a predetermined read voltage window. A test pulse is applied to the memory cell if it is determined that the threshold voltage has a value within the predetermined read voltage window. The state of the memory cell may be determined based on a response of the memory cell to the test pulse, wherein the state corresponds to the one of the pluralities of states of the memory cell prior to receiving the test pulse.

    Apparatuses and methods of reading memory cells
    57.
    发明授权
    Apparatuses and methods of reading memory cells 有权
    读取存储单元的设备和方法

    公开(公告)号：US09570167B2

    公开(公告)日：2017-02-14

    申请号：US14628824

    申请日：2015-02-23

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Innocenzo Tortorelli ,  Fabio Pellizzer ,  Ferdinando Bedeschi

    IPC: G11C13/00

    CPC classification number: G11C13/004 ,  G11C13/0004 ,  G11C13/0028 ,  G11C13/0033 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0047 ,  G11C2013/0057 ,  G11C2213/72

    Abstract: A method is provided for a reading memory even if there is a threshold voltage in an overlapped threshold voltage (VTH) region between a first state distribution and a second state distribution. The method includes ramping a bias on a memory cell a first time to determine a first threshold voltage (VTH1) of the memory cell and determining whether the VTH1 is within the overlapped VTH region. Upon determination that the memory cell is within the overlapped VTH region, the method further includes applying a write pulse to the memory cell; ramping a bias on the memory cell a second time to determine a second threshold voltage (VTH2); and determining the state of the memory cell prior to receiving the write pulse based on a comparison between the VTH1 and the VTH2.

    Abstract translation: 即使在第一状态分布和第二状态分布之间的重叠阈值电压（VTH）区域中存在阈值电压，也为读取存储器提供了一种方法。 该方法包括首先对存储器单元上的偏置进行斜坡以确定存储器单元的第一阈值电压（VTH1），并确定VTH1是否在重叠的VTH区域内。 当确定存储器单元位于重叠的VTH区域内时，该方法还包括向存储器单元施加写入脉冲; 第二次使存储器单元上的偏置斜坡以确定第二阈值电压（VTH2）; 以及基于VTH1和VTH2之间的比较，在接收到写脉冲之前确定存储单元的状态。

    Memory Cells, Memory Arrays, and Methods of Forming Memory Cells and Arrays
    58.
    发明申请
    Memory Cells, Memory Arrays, and Methods of Forming Memory Cells and Arrays 有权
    内存单元，内存阵列和形成内存单元和阵列的方法

    公开(公告)号：US20170018708A1

    公开(公告)日：2017-01-19

    申请号：US15279158

    申请日：2016-09-28

    Applicant: Micron Technology, Inc.

    Inventor： Andrea Redaelli ,  Giorgio Servalli ,  Carmela Cupeta ,  Fabio Pellizzer

    IPC: H01L45/00 ,  H01L27/24

    CPC classification number: H01L45/1293 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/065 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1286 ,  H01L45/141 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/1666 ,  H01L45/1675

    Abstract: Some embodiments include methods of forming memory cells. Heater structures are formed over an array of electrical nodes, and phase change material is formed across the heater structures. The phase change material is patterned into a plurality of confined structures, with the confined structures being in one-to-one correspondence with the heater structures and being spaced from one another by one or more insulative materials that entirely laterally surround each of the confined structures. Some embodiments include memory arrays having heater structures over an array of electrical nodes. Confined phase change material structures are over the heater structures and in one-to-one correspondence with the heater structures. The confined phase change material structures are spaced from one another by one or more insulative materials that entirely laterally surround each of the confined phase change material structures.

    Abstract translation: 一些实施例包括形成存储器单元的方法。 加热器结构形成在电节点阵列上，相变材料跨过加热器结构形成。 相变材料被图案化成多个限制结构，其中限制结构与加热器结构一一对应，并且通过一个或多个完全横向围绕每个限制结构的绝缘材料彼此间隔开 。 一些实施例包括在电节点阵列上具有加热器结构的存储器阵列。 密闭相变材料结构在加热器结构之上，并且与加热器结构一一对应。 受限制的相变材料结构通过一个或多个完全横向围绕每个限定相变材料结构的绝缘材料彼此间隔开。

    Reference voltage generation apparatuses and methods
    60.
    发明授权
    Reference voltage generation apparatuses and methods 有权
    参考电压产生装置和方法

    公开(公告)号：US09460784B1

    公开(公告)日：2016-10-04

    申请号：US14693275

    申请日：2015-04-22

    Applicant: Micron Technology, Inc.

    Inventor： Fabio Pellizzer

    IPC: G11C11/00 ,  G11C13/00

    CPC classification number: G11C13/0038 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/003 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2213/76

    Abstract: A method and apparatuses for generating a reference voltage are disclosed. One example apparatus includes a current source coupled to a first power supply. The current source supplies a first current. A reference memory cell is coupled to the current source at a reference node. The reference memory cell has a select device comprising a chalcogenic semiconductor material. A clamp circuit is coupled between the reference memory cell and a second power supply. The clamp circuit is configured to control a second current such that when the first current and second current are substantially equal, the reference voltage generated at the reference node tracks a threshold voltage of the select device.

    Abstract translation: 公开了一种用于产生参考电压的方法和装置。 一个示例性设备包括耦合到第一电源的电流源。 电流源提供第一个电流。 参考存储器单元在参考节点处耦合到当前源。 参考存储单元具有包括硫属半导体材料的选择器件。 钳位电路耦合在参考存储单元和第二电源之间。 钳位电路被配置为控制第二电流，使得当第一电流和第二电流基本相等时，在参考节点处产生的参考电压跟踪选择装置的阈值电压。

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