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51.发明授权公开(公告)号：US11200959B1
公开(公告)日：2021-12-14
申请号：US16988343
申请日：2020-08-07
Applicant: Micron Technology, Inc.
Inventor： James Fitzpatrick , Sivagnanam Parthasarathy , Patrick Robert Khayat , AbdelHakim S. Alhussien
Abstract: A memory device to determine a voltage window to read soft bit data. For example, in response to a read command, the memory device can read a group of memory cells at a plurality of test voltages to determine signal and noise characteristics, which can be used to determine an optimized read voltage for reading hard bit data and a voltage window between a first voltage and a second voltage for reading soft bit data. The soft bit data identifies exclusive or (XOR) of results read from the group of memory cells at the first voltage and at the second voltage respective. The memory device can provide a response to the read command based on the hard bit data and the soft bit data.
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公开(公告)号：US20210350868A1
公开(公告)日：2021-11-11
申请号：US17313939
申请日：2021-05-06
Applicant: Micron Technology, Inc.
Inventor： Sivagnanam Parthasarathy , James Fitzpatrick , Patrick Robert Khayat , AbdelHakim S. Alhussien
Abstract: A memory device to program a group of memory cells to store multiple bits per memory cell. Each bit per memory cell in the group from a page. After determining a plurality of read voltages of the group of memory cells, the memory device can read the multiple pages of the group using the plurality of read voltages. For each respective page in the multiple pages, the memory device can determine a count of first memory cells in the respective page that have threshold voltages higher than a highest read voltage, among the plurality of read voltages, used to read the respective page. The count of the first memory cells can be compared with a predetermined range of a fraction of memory cells in the respective page to evaluate the plurality of read voltages (e.g., whether any of the read voltages is in a wrong voltage range).
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公开(公告)号：US20210311668A1
公开(公告)日：2021-10-07
申请号：US17350425
申请日：2021-06-17
Applicant: Micron Technology, Inc.
Inventor： AbdelHakim S. Alhussien , Sivagnanam Parthasarathy , James Fitzpatrick , Patrick Robert Khayat
Abstract: A memory sub-system configured to iterative calibrate read voltages, where higher read voltages are calibrated based on the calibration results of lower read voltages. For example, a memory device initially determines first read voltages of a group of memory cells. The memory device calculates a second read voltage optimized to read the group of memory cells according to first signal and noise characteristics measured based on at least one of the first read voltages. A third read voltage is estimated based on an offset of the second read voltage from a corresponding voltage among the first read voltages. Second signal and noise characteristics of the group of memory cells are measured based on the third read voltage. The memory device then calculates a fourth read voltage optimized to read the group of memory cells according to the second signal and noise characteristics.
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公开(公告)号：US20210273650A1
公开(公告)日：2021-09-02
申请号：US16807065
申请日：2020-03-02
Applicant: Micron Technology, Inc.
Inventor： Sivagnanam Parthasarathy , James Fitzpatrick , Patrick Robert Khayat , AbdelHakim S. Alhussien
Abstract: A memory sub-system configured to: measure a plurality of sets of signal and noise characteristics of a group of memory cells in a memory device; determine a plurality of optimized read voltages of the group of memory cells from the plurality of sets of signal and noise characteristics respectively; generate features from the plurality of sets of signal and noise characteristics, including at least one compound feature generated from the plurality of sets of signal and noise characteristics; generate, using the features, a classification of a bit error rate of data retrievable from the group of memory cells; and control an operation to read the group of memory cells based on the classification.
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公开(公告)号：US12217803B2
公开(公告)日：2025-02-04
申请号：US17742345
申请日：2022-05-11
Applicant: Micron Technology, Inc.
Inventor： Abdelhakim S. Alhussien , James Fitzpatrick , Patrick Robert Khayat , Sivagnanam Parthasarathy
Abstract: A memory device to determine a voltage optimized to read a group of memory cells. In response to a command, the memory device reads the group of memory cells at a plurality of test voltages to determine a set of signal and noise characteristics of the group of memory cells. The memory device determines or recognizes a shape of a distribution of the signal and noise characteristics over the plurality of test voltages. Based on the shape, the memory device selects an operation in determining an optimized read voltage of the group of memory cells.
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Patent Agency Ranking
公开(公告)号：US12131060B2
公开(公告)日：2024-10-29
申请号：US17872426
申请日：2022-07-25
Applicant: Micron Technology, Inc.
Inventor： Kishore Kumar Muchherla , Dung V. Nguyen , Dave Scott Ebsen , Tomoharu Tanaka , James Fitzpatrick , Huai-Yuan Tseng , Akira Goda , Eric N. Lee
IPC: G06F3/06
CPC classification number: G06F3/0655 , G06F3/0604 , G06F3/064 , G06F3/0679
Abstract: Exemplary methods, apparatuses, and systems include a quick charge loss (QCL) mitigation manager for controlling writing data bits to a memory device. The QCL mitigation manager receives a first set of data bits for programming to memory. The QCL mitigation manager writes a first subset of data bits of the first set of data bits to a first memory block of the memory during a first pass of programming. The QCL mitigation manager writes a second subset of data bits of the first set of data bits to the first memory block during a second pass of programming in response to determining that the threshold delay is satisfied.
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公开(公告)号：US12105961B2
公开(公告)日：2024-10-01
申请号：US17978890
申请日：2022-11-01
Applicant: Micron Technology, Inc.
Inventor： Jeffrey S. McNeil , Sivagnanam Parthasarathy , Kishore Kumar Muchherla , Patrick R. Khayat , Sead Zildzic , Violante Moschiano , James Fitzpatrick
CPC classification number: G06F3/0611 , G06F3/064 , G06F3/0679 , G11C16/3459 , G11C29/52
Abstract: A method includes receiving, by control logic of a memory device, a copyback clear command from a processing device; causing, in response to the copyback clear command, a page buffer to perform a dual-strobe read operation on first memory cells configured as single-level cells, the dual-strobe read operation including a soft strobe at a first threshold voltage and a hard strobe at a second threshold voltage that are sensed between threshold voltage distributions of the first memory cells; causing the page buffer to determine a number of one bit values within the threshold voltage distributions detected in a threshold voltage range between the first/second threshold voltages; and causing, in response to the number of one bit values not satisfying a threshold criterion, a copyback of data in the first memory cells to second memory cells configured as high-level cells without intervention from the processing device.
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公开(公告)号：US12073891B2
公开(公告)日：2024-08-27
申请号：US17682089
申请日：2022-02-28
Applicant: Micron Technology, Inc.
Inventor： Eric N. Lee , Violante Moschiano , Jeffrey S. McNeil , James Fitzpatrick , Sivagnanam Parthasarathy , Kishore Kumar Muchherla , Patrick R. Khayat
CPC classification number: G11C16/30 , G11C16/102 , G11C16/26 , G11C2207/2254
Abstract: Processing logic in a memory device receives a command to execute a set of read operations having read voltage levels corresponding to a programming distribution associated with the memory device. A set of memory bit counts is determined, where each memory bit count corresponds to a respective bin of a set of bins associated with the multiple read voltage levels of the set of read operations. A valley center bin having a minimum memory bit count of the set of memory bit counts is determined. The processing logic determines that the minimum memory bit count of the valley center bin satisfies a condition and an adjusted read voltage level associated with the valley center bin is identified in response to the condition being satisfied.
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59.发明公开公开(公告)号：US20240265979A1
公开(公告)日：2024-08-08
申请号：US18636901
申请日：2024-04-16
Applicant: Micron Technology, Inc.
Inventor： James Fitzpatrick , Phong Sy Nguyen , Dung Viet Nguyen , Sivagnanam Parthasarathy
CPC classification number: G11C16/3404 , A63B24/0075 , G11C16/26 , A63B2024/0068 , A63B2024/0093 , A63B2220/836 , A63B2230/06
Abstract: A memory system configured to dynamically adjust the amount of redundant information stored in memory cells of a wordline on an integrated circuit die based on a bit error rate. For example, in response to a determination that a bit error rate of the wordline is above a threshold, the memory system can store first data items as independent first codewords of an error correction code technique into a first portion of the memory cells of the wordline, generate second data items as redundant information from the first codewords, and store the second data items in a second portion of the memory cells of the wordline. If the bit error rate is below the threshold, third data items can be stored as independent second codewords of the same length as the first codewords in the memory cells of the wordline.
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公开(公告)号：US20240232013A1
公开(公告)日：2024-07-11
申请号：US18611450
申请日：2024-03-20
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Kishore Kumar Muchherla , Niccolo’ Righetti , Sivagnanam Parthasarathy , Mustafa N. Kaynak , Mark A. Helm , James Fitzpatrick , Ugo Russo
CPC classification number: G06F11/1068 , G06F11/076 , G06F11/1435
Abstract: A method includes determining, by a processing device, a value of a memory endurance state metric associated with a segment of a memory device in a memory sub-system; determining a target value of a code rate based on the value of the memory endurance state metric, and adjusting the code rate of the memory device according to the target value, wherein the code rate reflects a ratio of a number of memory units designated for storing host-originated data to a total number of memory units designated for storing the host-originated data and error correction metadata.
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