中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

69 records (took 0.026 seconds)

    Program command generation with dummy data generation at a memory device
    51.
    发明授权
    Program command generation with dummy data generation at a memory device 有权

    公开(公告)号：US12141437B2

    公开(公告)日：2024-11-12

    申请号：US17974799

    申请日：2022-10-27

    Applicant: Micron Technology, Inc.

    Inventor： Jeremy Binfet ,  Violante Moschiano ,  James Fitzpatrick ,  Kishore Kumar Muccherla ,  Jeffrey S. McNeil ,  Phong Sy Nguyen

    IPC: G06F3/06

    Abstract: A memory device comprising an array of memory cells organized into a set of sub-blocks and a set of wordlines. Control logic is operatively coupled with the array of memory cells, the control logic to perform operations including: receiving a program command from a processing device, the program command including information indicative of a physical address associated with a retired wordline of the set of wordlines; in response to detecting the information within the program command, generating dummy data that is one of pseudo-random data, all one values, or all zero values; and causing the dummy data to be programmed to memory cells of multiple sub-blocks of the set of sub-blocks that are selectively connected to the retired wordline.

    Peak power management self-check
    57.
    发明授权
    Peak power management self-check 有权

    公开(公告)号：US11670395B2

    公开(公告)日：2023-06-06

    申请号：US17249400

    申请日：2021-03-01

    Applicant: Micron Technology, Inc.

    Inventor： Jeremy Binfet ,  Liang Yu

    IPC: G11C29/00 ,  G11C29/50 ,  G06F1/3225

    CPC classification number: G11C29/50 ,  G06F1/3225

    Abstract: A memory device includes a first memory die of a plurality of memory dies, the first memory die comprising a first memory array and a first power management component, wherein the first power management component is configured to send a first test value to one or more other power management components on one or more other memory dies of the plurality of memory dies during a first power management cycle of a first power management token loop. The memory device further includes a second memory die of the plurality of memory dies, the second memory die comprising a second memory array and a second power management component, wherein the second power management component is configured to receive the first test value from the first power management component during the first power management cycle of the first power management token loop and send a second test value to the one or more other power management components on the one or more other memory dies of the plurality of memory dies during a second power management cycle of a second power management token loop. At least one of the first power management component or the second power management component is configured to compare the first test value and the second test value to a set of expected values to determine whether signal connections between the first power management component and the second power management component are functional.

    MEMORY PLANE ACCESS MANAGMENT
    59.
    发明申请
    MEMORY PLANE ACCESS MANAGMENT 有权

    公开(公告)号：US20230070445A1

    公开(公告)日：2023-03-09

    申请号：US17984916

    申请日：2022-11-10

    Applicant: Micron Technology, Inc.

    Inventor： Eric N. Lee ,  Robert W. Strong ,  William Akin ,  Jeremy Binfet

    IPC: G11C16/04 ,  G11C16/30 ,  G11C16/22 ,  G11C16/24 ,  G11C16/34

    Abstract: A method includes identifying a target plane in respective planes of a memory die in a non-volatile memory array and identifying, from blocks of non-volatile memory cells coupled to a common bit line in the target plane, at least one target block in the target plane. The method further includes performing an operation to disable at least one gate associated with the at least one target block to prevent access to the blocks of non-volatile memory cells coupled to the common bit line in the target plane.

Patent Agency Ranking