公开(公告)号：US20240045914A1

公开(公告)日：2024-02-08

申请号：US18223931

申请日：2023-07-19

Applicant: Micron Technology, Inc.

Inventor： Chiara Cerafogli ,  Jonathan S. Parry

IPC: G06F16/9535 ,  G06F16/9538

CPC classification number: G06F16/9535 ,  G06F16/9538

Abstract: Processing logic maintains a data item tag hierarchy in view of user context information and identifies, from the data item tag hierarchy, a highest ranked data item tag of a plurality of data item tags associated with a data item, the plurality of data item tags representing a content of the data item. The processing logic further storing the data item on a memory device at a first shared storage location together with one or more additional data items with which the highest ranked data item tag is also associated.

公开(公告)号：US20240028521A1

公开(公告)日：2024-01-25

申请号：US18211476

申请日：2023-06-19

Applicant: Micron Technology, Inc.

Inventor： Giuseppe Cariello ,  Jonathan S. Parry

IPC: G06F12/10 ,  G11C16/04 ,  G11C16/26 ,  G11C16/10

CPC classification number: G06F12/10 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/10 ,  G11C2216/14 ,  G06F2212/657

Abstract: Methods, systems, and devices for dual address encoding for logical-to-physical mapping are described. A memory device may identify a first physical address corresponding to a first logical block address generated by a host device and a second physical address corresponding to a second (consecutive) logical block address generated by a host device. The memory device may store the first physical address and second physical address in a single entry of a logical-to-physical mapping table that corresponds to the first logical block address. The memory device may transmit the logical-to-physical table to the host device for storage at the host device. The host device may subsequently transmit a single read command to the memory device that includes the first physical address and the second physical address based on the logical-to-physical table.

公开(公告)号：US20230359552A1

公开(公告)日：2023-11-09

申请号：US17633525

申请日：2021-03-18

Applicant: Micron Technology, Inc.

Inventor： Bin Zhao ,  Jonathan S. Parry ,  Deping He ,  Xu Zhang

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/7201

Abstract: Methods, systems, and devices for memory write performance techniques are described. A memory system may receive a sequence of commands, for example from a host system. Based on a relationship between logical block addresses of the sequence of commands, the memory system may delay performing a memory management operation (e.g., a garbage collection procedure, a power operation, a cache synchronization operation, a data relocation operation, or the like) for a duration. For example, the memory system may determine whether a quantity of write commands in the sequence that include non-consecutive logical block addresses exceeds a threshold. In some cases, the memory system may perform one or more commands in the sequence during the duration. Subsequently (e.g., at the end of the duration), the memory system may perform the memory management operation.

公开(公告)号：US20230305617A1

公开(公告)日：2023-09-28

申请号：US18096288

申请日：2023-01-12

Applicant: Micron Technology, Inc.

Inventor： Luca Porzio ,  Christian M. Gyllenskog ,  Giuseppe Cariello ,  Marco Onorato ,  Roberto IZZI ,  Stephen Hanna ,  Jonathan S. Parry ,  Reshmi Basu ,  Nadav Grosz ,  David Aaron Palmer

IPC: G06F1/3234 ,  G06F9/4401 ,  G06F1/324

CPC classification number: G06F1/3275 ,  G06F1/324 ,  G06F9/4411

Abstract: Methods, systems, and devices for dynamic power modes for boot-up procedures are described. A memory system may initiate a boot-up procedure according to a predefined first power mode that is associated with a first power consumption. The memory system may then determine whether to perform the boot-up procedure according to the first power mode or a second power mode associated with a different second power consumption. In cases that the memory system receives an indication of the second power mode from the host system, the memory system may perform the boot-up procedure according to the second power mode. Additionally, in cases that the memory system does not receive an indication of the second power mode from the host system, the memory system may perform the boot-up procedure according to the first power mode.

公开(公告)号：US20230289062A1

公开(公告)日：2023-09-14

申请号：US18121494

申请日：2023-03-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jeffrey S. McNeil ,  Jonathan S. Parry ,  Ugo Russo ,  Akira Goda ,  Kishore Kumar Muchherla ,  Violante Moschiano ,  Niccolo' Righetti ,  Silvia Beltrami

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0659 ,  G06F3/0679

Abstract: Control logic in a memory device causes a first pulse to be applied to a plurality of word lines coupled to respective memory cells in a memory array during an erase operation. The control logic further causes a second pulse to be applied to a first set of word lines of the plurality of word lines to bias the first set of word lines to a first voltage. The control logic can cause a third pulse to be applied to a second set of word lines of the plurality of word lines to bias the second set of word lines to a second voltage and cause a fourth pulse to be applied to a source line of the memory array to erase the respective memory cells coupled to the first set of word lines and to program the respective memory cells coupled to the second set of word lines.

公开(公告)号：US20230195312A1

公开(公告)日：2023-06-22

申请号：US17990126

申请日：2022-11-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Liang Yu ,  Jonathan S. Parry ,  Fumin Gu ,  John Paul Aglubat

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0634 ,  G06F3/0679

Abstract: A memory device includes memory dies, each memory die including a memory array and control logic, operatively coupled with the memory array, to perform peak power management (PPM) operations. The PPM operations include causing a memory die to be placed in a suspended state to suspend execution of a first media access operation with a reserved current budget, receiving a set of requests to execute at least a second media access operation during the suspended state, and in response receiving the set of requests, handling the set of requests by implementing current budget arbitration logic with respect to the reserved current budget.

公开(公告)号：US20230087329A1

公开(公告)日：2023-03-23

申请号：US18053201

申请日：2022-11-07

Applicant: Micron Technology, Inc.

Inventor： Timothy B. Cowles ,  George B. Raad ,  James S. Rehmeyer ,  Jonathan S. Parry

IPC: G11C16/14 ,  G11C16/30 ,  G11C17/16 ,  G11C17/18 ,  G11C16/22 ,  G11C13/00 ,  G11C11/16 ,  G11C11/22 ,  G11C16/08

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices and systems are provided, in which at least a subset of a non-volatile memory array is configured to behave as a volatile memory by erasing or degrading data in the event of a changed power condition such as a power-loss event, a power-off event, or a power-on event. In one embodiment of the present technology, a memory device is provided, comprising a non-volatile memory array, and circuitry configured to store one or more addresses of the non-volatile memory array, to detect a changed power condition of the memory device, and to erase or degrade data at the one or more addresses in response to detecting the changed power condition.

公开(公告)号：US20230060859A1

公开(公告)日：2023-03-02

申请号：US17462305

申请日：2021-08-31

Applicant: Micron Technology, Inc.

Inventor： Jonathan S. Parry ,  Jeffrey S. McNeil ,  Giuseppe Cariello ,  Kishore Kumar Muchherla ,  Reshmi Basu

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/26

Abstract: Methods, systems, and devices for overwriting at a memory system are described. A memory system may be configured to overwrite portions of a memory array with new data, which may be associated with omitting an erase operation. For example, write operations may be performed in accordance with a first demarcation configuration to store information at a portion of a memory array. A portion of a memory system may then determine to overwrite the portion of the memory array with different or updated information, which may include performing write operations in accordance with a second demarcation configuration. The second demarcation configuration may be associated with different cell characteristics for a one or more logic states, such as different distributions of stored charge or other cell property, different demarcation characteristics, different write operations, among other differences, which may support performing an overwrite operation without first performing an erase operation.

公开(公告)号：US20230060200A1

公开(公告)日：2023-03-02

申请号：US17649268

申请日：2022-01-28

Applicant: Micron Technology, Inc.

Inventor： Jonathan S. Parry ,  Christian M. Gyllenskog ,  Luca Porzio

IPC: G06F3/06

Abstract: Methods, systems, and devices for suspend operation with data transfer to a host system are described. A host system may transmit a read command to a memory system operating in a first mode of operation (e.g., a standard mode associated with a nominal power consumption) indicating for the memory system to transition to a second mode of operation (e.g., a suspend mode associated with a decreased power consumption). Here, the memory system may transmit an image of the memory system stored in volatile memory to the host system and transition the memory system to the second mode. Additionally, the host system may transmit, to the memory system operating in the second mode, a write command including the image and indicating for the memory system to transition to the first mode. Here, the memory system may write the image to the volatile memory and transition to the first mode.

公开(公告)号：US20230040336A1

公开(公告)日：2023-02-09

申请号：US17396117

申请日：2021-08-06

Applicant: Micron Technology, Inc.

Inventor： Reshmi Basu ,  David Aaron Palmer ,  Jonathan S. Parry

IPC: G06F3/06 ,  G06F1/08

Abstract: Methods, systems, and devices for adaptive throughput monitoring are described. In some examples, a memory system may be associated with one or more clocks that are each associated with a respective subcomponent. When the memory system receives a plurality of commands, the memory system may determine a throughput of the commands. Based on the determined throughput, the memory system may adjust a rate of one or more of the clocks.