公开(公告)号：US20200081769A1

公开(公告)日：2020-03-12

申请号：US16126991

申请日：2018-09-10

Applicant: Micron Technology, Inc.

Inventor： Yoshiro Riho ,  Atsushi Shimizu ,  Sang-Kyun Park ,  Jongtae Kwak

IPC: G06F11/10 ,  G11C29/42 ,  G11C29/52 ,  H03M13/00

Abstract: Apparatuses and methods for error correction coding and data bus inversion for semiconductor memories are described. An example apparatus includes an I/O circuit configured to receive first data and first ECC data associated with the first data, a memory array, and a control circuit. The control circuit is coupled between the I/O circuit and the memory array. The control circuit is configured to execute first ECC-decoding to produce corrected first data and corrected first ECC data responsive, at least in part, to the first data and the first ECC data. The control circuit is further configured to store both the corrected first data and the corrected first ECC data into the memory array.

公开(公告)号：US20180247690A1

公开(公告)日：2018-08-30

申请号：US15445795

申请日：2017-02-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hyun Yoo Lee ,  Jongtae Kwak ,  Suryanarayana Tatapudi

IPC: G11C11/4076 ,  G11C11/408 ,  G11C11/4096 ,  G06F1/12 ,  G11C11/4093

CPC classification number: G11C7/00 ,  G06F1/12 ,  G11C7/10 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4093 ,  G11C11/4096 ,  G11C19/00

Abstract: In an example apparatus, a command path receives read commands and provides respective control signals for each read command. The command path is configured to provide initial control signals for an initial read command responsive to a first clock edge of a clock signal of a plurality of multiphase clock signals and to further provide respective control signals for subsequent read commands responsive to receipt of the subsequent read commands. The example apparatus further includes a read data output circuit configured to receive the control signals from the command path and further receive read data in parallel. The read data output circuit is configured to provide the read data serially responsive to the control signals.

公开(公告)号：US20170249985A1

公开(公告)日：2017-08-31

申请号：US15592436

申请日：2017-05-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Onegyun Na ,  Jongtae Kwak ,  Seong-Hoon Lee ,  Hoon Choi

IPC: G11C11/4091 ,  G11C11/4074

CPC classification number: G11C11/4091 ,  G11C7/02 ,  G11C7/06 ,  G11C7/062 ,  G11C7/065 ,  G11C11/4074 ,  G11C2207/063 ,  G11C2207/2281

Abstract: A current sense amplifier may include one or more clamping circuits coupled between differential output nodes of the amplifier. The clamping circuits may be enabled during at least a portion of the time that the sense amplifier is sensing the state of a memory cell coupled to a differential input of the sense amplifier. The clamping circuits may be disabled during the time that the sense amplifier is sensing the state of a memory cell at different times in a staggered manner. The clamping circuits may be effecting in making the current sense amplifier less sensitive to noise signals.

公开(公告)号：US20150302907A1

公开(公告)日：2015-10-22

申请号：US14254378

申请日：2014-04-16

Applicant: Micron Technology, Inc.

Inventor： Mark K. Hadrick ,  Jeffrey P. Wright ,  Victor Wong ,  Simon J. Lovett ,  Donald M. Morgan ,  William F. Jones ,  Sujeet Ayyapureddi ,  Dean D. Gans ,  Jongtae Kwak

IPC: G11C8/06 ,  G11C7/22

CPC classification number: G11C7/22 ,  G11C7/1009 ,  G11C7/1042 ,  G11C8/12 ,  G11C2207/229

Abstract: Apparatuses and methods for implementing masked write commands are disclosed herein. An example apparatus may include a memory bank, a local buffer circuit, and an address control circuit. The local buffer circuit may be associated with the memory bank. The address control circuit may be coupled to the memory bank and configured to receive a command and an address associated with the command. The address control circuit may include a global buffer circuit configured to store the address. The address control circuit may further be configured to delay the command using one of a plurality of command paths based, at least in part, on a write latency and to provide the address stored in the global buffer circuit to the local buffer circuit to be stored therein.

Abstract translation: 本文公开了用于实现屏蔽写入命令的装置和方法。 示例性装置可以包括存储体，局部缓冲电路和地址控制电路。 本地缓冲电路可以与存储体相关联。 地址控制电路可以耦合到存储体并被配置为接收命令和与命令相关联的地址。 地址控制电路可以包括被配置为存储地址的全局缓冲电路。 地址控制电路还可以被配置为至少部分地基于写等待时间来延迟使用多个命令路径之一的命令，并且将存储在全局缓冲器电路中的地址提供给要存储的本地缓冲器电路 其中。

公开(公告)号：US09000817B2

公开(公告)日：2015-04-07

申请号：US14046796

申请日：2013-10-04

Applicant: Micron Technology, Inc

Inventor： Jongtae Kwak ,  Kallol Mazumder

IPC: H03L7/00 ,  H03L7/08 ,  H03L7/081

CPC classification number: H03L7/08 ,  H03L7/0816

Abstract: Apparatuses and methods related to altering the timing of command signals for executing commands is disclosed. One such method includes calculating a forward path delay of a clock circuit in terms of a number of clock cycles of an output clock signal provided by the clock circuit and adding a number of additional clock cycles of delay to a forward path delay of a signal path. The forward path delay of the clock circuit is representative of the forward path delay of the signal path and the number of additional clock cycles is based at least in part on the number of clock cycles of forward path delay.

Abstract translation: 公开了与改变用于执行命令的命令信号的定时相关的装置和方法。 一种这样的方法包括根据由时钟电路提供的输出时钟信号的时钟周期的数量来计算时钟电路的前向路径延迟，并将多个延迟的附加时钟周期与信号路径的前向路径延迟相加 。 时钟电路的正向路径延迟表示信号路径的前向路径延迟，并且附加时钟周期的数量至少部分地基于前向路径延迟的时钟周期数。

公开(公告)号：US08879337B1

公开(公告)日：2014-11-04

申请号：US13867544

申请日：2013-04-22

Applicant: Micron Technology, Inc.

Inventor： Jongtae Kwak

IPC: G11C7/10 ,  G11C7/22

CPC classification number: G11C7/106 ,  G11C7/1018 ,  G11C7/1066 ,  G11C7/222

Abstract: A memory, a system and a method for controlling dynamic burst length control data can generate clocks for both an upstream counter and a downstream counter by using substantially the same latency delayed received command indications. A downstream clock generation circuit generates a clock signal from a received command indication delayed by both a delay locked loop and latency delays stored in latency control circuits. An upstream clock generation circuit generates a clock signal from the received command indication delayed by the delay locked loop and capture indications from the latency control circuits.

Abstract translation: 用于控制动态突发长度控制数据的存储器，系统和方法可以通过使用基本上相同的等待时间延迟的接收命令指示来为上游计数器和下游计数器产生时钟。 下行时钟产生电路从延迟锁定环路延迟的接收到的命令指示和等待时间控制电路中存储的等待时延延迟生成时钟信号。 上行时钟发生电路根据延迟锁定环延迟的接收命令指示产生时钟信号，并从等待时间控制电路捕获指示。