公开(公告)号：US12087394B2

公开(公告)日：2024-09-10

申请号：US17930655

申请日：2022-09-08

Applicant: Micron Technology, Inc.

Inventor： Brian W. Huber ,  Scott E. Smith ,  Gary L. Howe

IPC: G11C7/10

CPC classification number: G11C7/1084 ,  G11C7/109 ,  G11C7/1093 ,  G11C7/1096

Abstract: A memory device includes a command interface configured to receive write commands from a host device. Additionally, the memory device includes an input buffer configured to buffer a strobe signal from the host device. Furthermore, the memory device includes a first ripple counter and a second ripple counter. The memory device includes command handling circuitry configured to alternatingly start the first ripple counter and the second ripple counter in response to consecutive write commands. The command handling circuitry and/or the first and second ripple counters are configured to suppress a reset of the input buffer if either the first ripple counter or the second ripple counter has not reached a threshold and is still counting.

公开(公告)号：US20240161859A1

公开(公告)日：2024-05-16

申请号：US18504353

申请日：2023-11-08

Applicant: Micron Technology, Inc.

Inventor： Sujeet Ayyapureddi ,  Scott E. Smith

IPC: G11C29/52 ,  G11C7/10 ,  G11C7/12 ,  G11C29/00

CPC classification number: G11C29/52 ,  G11C7/1096 ,  G11C7/12 ,  G11C29/785

Abstract: Apparatuses, systems, and methods for separate write enable signals for data, metadata, and parity information. A memory array is divided into column planes and an extra column plane. In some modes of the memory device, data and parity information is stored in the column planes and metadata is stored in the extra column plane. The extra column plane includes separate write enable signals (or separate states of a single signal) which activate different portions of the bit lines (e.g., even and odd bit lines). In an example access operation, a column select signal is provided to the extra column plane along with one or the other write enable signals such that fewer than all of the bit lines activated by the column select signal provide data.

公开(公告)号：US20240087621A1

公开(公告)日：2024-03-14

申请号：US17930655

申请日：2022-09-08

Applicant: Micron Technology, Inc.

Inventor： Brian W. Huber ,  Scott E. Smith ,  Gary L. Howe

IPC: G11C7/10

CPC classification number: G11C7/1084 ,  G11C7/109 ,  G11C7/1093 ,  G11C7/1096

Abstract: A memory device includes a command interface configured to receive write commands from a host device. Additionally, the memory device includes an input buffer configured to buffer a strobe signal from the host device. Furthermore, the memory device includes a first ripple counter and a second ripple counter. The memory device includes command handling circuitry configured to alternatingly start the first ripple counter and the second ripple counter in response to consecutive write commands. The command handling circuitry and/or the first and second ripple counters are configured to suppress a reset of the input buffer if either the first ripple counter or the second ripple counter has not reached a threshold and is still counting.

公开(公告)号：US11848070B2

公开(公告)日：2023-12-19

申请号：US17523312

申请日：2021-11-10

Applicant: Micron Technology, Inc.

Inventor： Mijo Kim ,  Scott E. Smith ,  Si Hong Kim

IPC: G11C7/10 ,  G11C8/18 ,  G11C7/20

CPC classification number: G11C7/1093 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1087 ,  G11C7/20 ,  G11C8/18

Abstract: Memory with DQS pulse control circuitry is disclosed herein. In one embodiment, a memory device comprises a DQS terminal and circuitry operably coupled to the DQS terminal. The DQS terminal is configured to receive an external DQS signal including a first pulse having a first width. In turn, the circuitry is configured to generate a second pulse based at least in part on the first pulse and output an internal DQS signal including the second pulse. The second pulse can have a second width greater than the first width. In some embodiments, the external DQS signal can further include a third pulse having a third width greater than the second width. In such embodiments, the circuitry can be further configured to generate and output a fourth pulse based at least in part on the third pulse that has a fourth width equivalent to the third width.

公开(公告)号：US20230229348A1

公开(公告)日：2023-07-20

申请号：US17648513

申请日：2022-01-20

Applicant: Micron Technology, Inc.

Inventor： Sujeet V. Ayyapureddi ,  Scott E. Smith

IPC: G06F3/06

CPC classification number: G06F3/0656 ,  G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

Abstract: Methods, systems, and devices for metadata implementation for memory devices are described. A memory device may read metadata, transfer the metadata to a buffer, and read information. For example, the memory device may receive a read command from a host device to read information. The memory device may execute a first internal read command to read the metadata associated with the information. Upon reading the metadata, the memory device may store the metadata in the buffer (e.g., one or more latches). Upon determining that a duration has elapsed, the memory device may execute a second internal read command to read the information associated with the metadata. The memory device transmits the information and the metadata to the host device. In some other cases, the memory device may write information, store metadata in a buffer, and write the metadata (e.g., a different order than for read operations).

公开(公告)号：US20230206986A1

公开(公告)日：2023-06-29

申请号：US17746757

申请日：2022-05-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Noriaki Mochida ,  Takayuki Miyamoto ,  Kallol Mazumder ,  Scott E. Smith

IPC: G11C11/4076 ,  G11C11/4093

CPC classification number: G11C11/4076 ,  G11C11/4093

Abstract: An exemplary semiconductor device includes an internal clock circuit configured to intermittently enable and disable a clock signal while in a Maximum Power Savings Mode. The duty cycle of the enablement and disablement of the clock signal may be based on susceptibility to negative-bias temperature instability of a component of the semiconductor device. The clock signal may be enabled and disabled via a synchronizer.

公开(公告)号：US20230121163A1

公开(公告)日：2023-04-20

申请号：US17505122

申请日：2021-10-19

Applicant: Micron Technology, Inc.

Inventor： Scott E. Smith ,  Randy Brian Drake ,  Brian Ladner ,  Thanh Kim Mai ,  Sujeet Ayyapureddi ,  Matthew Alan Prather

IPC: G06F13/40 ,  G06F13/16 ,  G06F11/10

Abstract: The systems and methods described herein relate to a bi-directional data path (DQ) symbol map generated based on error correction operations. A device may include sub-wordline drivers and bi-directional data paths (DQs) that couple between the sub-wordline drivers and input/output (I/O) interface circuitry based on assignments indicated by the DQ symbol map. The assignments may be generated based on error correction operations performed on data of the memory bank. In particular, the DQ symbol map may be generated to avoid some conditions that, if occurring, may render one or more data errors uncorrectable. These systems and methods may reduce a likelihood of a data error associated with a DQ being uncorrectable.

公开(公告)号：US11430504B2

公开(公告)日：2022-08-30

申请号：US17005034

申请日：2020-08-27

Applicant: Micron Technology, Inc.

Inventor： Miles S. Wiscombe ,  Scott E. Smith ,  Gary L. Howe ,  Brian W. Huber ,  Tony M. Brewer

IPC: G06F13/28 ,  G11C11/408 ,  G11C11/4096 ,  G11C11/406 ,  G11C11/4094

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which memory devices are configured to provide row clear features. In some embodiments, the memory device may receive a command from a host device directed to a row of a memory array included in the memory device. The memory device may determine that the command is directed to two or more columns associated with the row, where each column is coupled with a group of memory cells. The memory device may activate the row to write the two or more columns using a set of predetermined data stored in a register of the memory device. Subsequently, the memory device may deactivate the word line based on writing the set of predetermined data to the two or more columns.

公开(公告)号：US20210295917A1

公开(公告)日：2021-09-23

申请号：US17342116

申请日：2021-06-08

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Gary L. Howe ,  Scott E. Smith

IPC: G11C16/08 ,  G11C7/06 ,  G11C8/10

Abstract: Apparatuses and methods for decoding addresses for memory are disclosed. An example apparatus includes a memory cell array and a row decoder. The memory cell array includes a bank of memory including a plurality of groups of memory. Each of the groups of memory includes sections of memory, and each of the sections of memory including memory cells arranged in rows and columns of memory. The row decoder decodes addresses to access a first group of memory to include rows of prime memory from a first block of memory and to include rows of prime memory from a second block of memory. The row decoder decodes the addresses to access a second group of memory to include rows of prime memory from the second block of memory and to include rows of redundant memory. The rows of redundant memory are shared with the first and second blocks of memory.

公开(公告)号：US11042436B2

公开(公告)日：2021-06-22

申请号：US16554913

申请日：2019-08-29

Applicant: Micron Technology, Inc.

Inventor： Aaron Jannusch ,  Brett K. Dodds ,  Debra M. Bell ,  Joshua E. Alzheimer ,  Scott E. Smith

IPC: G11C29/00 ,  G06F11/10

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which a host device may access a group of memory cells (e.g., portion of an array configurable to store ECC parity bits) otherwise reserved for ECC functionality of a memory device. The memory device may include a register to indicate whether its ECC functionality is enabled or disabled. When the register indicates the ECC functionality is disabled, the memory device may increase a storage capacity available to the host device by making the group of memory cells available for user-accessible data. Additionally or alternatively, the memory device may store metadata associated with various operational aspects of the memory device in the group of memory cells. Moreover, the memory device may modify a burst length to accommodate additional information to be stored in or read from the group of memory cells.