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    Memory device and method of operation
    52.
    发明授权
    Memory device and method of operation 有权

    公开(公告)号：US10446236B1

    公开(公告)日：2019-10-15

    申请号：US16021964

    申请日：2018-06-28

    Applicant: Micron Technology, Inc.

    Inventor： Shigekazu Yamada

    IPC: G11C16/08 ,  G11C16/30 ,  G11C16/04 ,  G11C16/14 ,  G11C16/26 ,  G11C16/10 ,  G11C16/32

    Abstract: Discussed herein are systems and methods for charging an access line to a non-volatile memory cell during a standby state, such as to prevent or mitigate standby-state charge loss. An embodiment of a memory device comprises a memory cell, a string driver circuit, and a charging circuit. The stringer driver circuit is coupled to the memory cell via a local word line, and has a common p-well. The charging circuit, in response to a voltage of a global word line of the memory device falling below a reference voltage during a standby state, couple a supply voltage to the common p-well of the string driver circuit to charge the global word line to a positive bias potential. The memory device includes a leakage compensation circuit to compensate for the junction leakage.

    SEMICONDUCTOR MEMORY COLUMN DECODER DEVICE AND METHOD
    55.
    发明申请
    SEMICONDUCTOR MEMORY COLUMN DECODER DEVICE AND METHOD 审中-公开

    公开(公告)号：US20180342299A1

    公开(公告)日：2018-11-29

    申请号：US16036578

    申请日：2018-07-16

    Applicant: Micron Technology, Inc.

    Inventor： Shigekazu Yamada ,  TOMOHARU TANAKA

    IPC: G11C16/14 ,  G11C16/16 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26

    Abstract: Semiconductor memory devices and methods include a flash memory cell array fabricated in a well, with memory cells in the same column connected to each other in series and connected to a respective bit line. The memory devices also include a column decoder, a data register buffer unit, a row decoder, an erase control unit, and an input/output buffer unit. In one or more embodiments, the erase control unit applies voltages to the well to erase the memory cells in a manner that avoids breaking down p-n junctions formed by transistors fabricated in the well. In another embodiment, high voltage transistors are used to selectively isolate the bit lines from and couple the bit lines to a peripheral circuit in pairs so that each high voltage transistor is shared by two bit lines.

    Apparatuses, integrated circuits, and methods for measuring leakage current
    57.
    发明授权
    Apparatuses, integrated circuits, and methods for measuring leakage current 有权
    仪器，集成电路和测量漏电流的方法

    公开(公告)号：US09183948B2

    公开(公告)日：2015-11-10

    申请号：US14514218

    申请日：2014-10-14

    Applicant: Micron Technology, Inc.

    Inventor： Shigekazu Yamada

    IPC: G11C29/00 ,  G11C29/02 ,  G11C8/08 ,  G11C29/12 ,  G11C29/50

    CPC classification number: G11C29/025 ,  G11C8/08 ,  G11C2029/1202 ,  G11C2029/5006

    Abstract: Methods, apparatuses, and integrated circuits for measuring leakage current are disclosed. In one such example method, a word line is charged to a first voltage, and a measurement node is charged to a second voltage, the second voltage being less than the first voltage. The measurement node is proportionally coupled to the word line. A voltage on the measurement node is compared with a reference voltage. A signal is generated, the signal being indicative of the comparison. Whether a leakage current of the word line is acceptable or not can be determined based on the signal.

    Abstract translation: 公开了用于测量泄漏电流的方法，装置和集成电路。 在一个这样的示例方法中，字线被充电到第一电压，并且测量节点被充电到第二电压，第二电压小于第一电压。 测量节点按比例耦合到字线。 将测量节点上的电压与参考电压进行比较。 产生信号，该信号表示比较。 可以基于该信号来确定字线的泄漏电流是否可接受。

    APPARATUSES AND METHODS TO CONTROL BODY POTENTIAL IN MEMORY OPERATIONS
    58.
    发明申请
    APPARATUSES AND METHODS TO CONTROL BODY POTENTIAL IN MEMORY OPERATIONS 有权
    用于控制存储器操作中的身体潜力的装置和方法

    公开(公告)号：US20140160851A1

    公开(公告)日：2014-06-12

    申请号：US13707067

    申请日：2012-12-06

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Han Zhao ,  Akira Goda ,  Krishna K. Parat ,  Aurelio Giancarlo Mauri ,  Haitao Liu ,  Toru Tanzawa ,  Shigekazu Yamada ,  Koji Sakui

    IPC: G11C16/06

    CPC classification number: G11C16/3459 ,  G11C8/08 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/08 ,  G11C16/16 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3445 ,  G11C2213/71

    Abstract: Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatus and a data line coupled to the memory cell string. The memory cell string includes a pillar body associated with the memory cells. At least one of such apparatus can include a module configured to store information in a memory cell among memory cells and/or to determine a value of information stored in a memory cell among memory cells. The module can also be configured to apply a voltage having a positive value to the data line and/or a source to control a potential of the body. Other embodiments are described.

    Abstract translation: 一些实施例包括具有存储单元串的装置和方法，所述存储单元串包括位于装置的不同级别中的存储器单元和耦合到存储单元串的数据线。 存储单元串包括与存储单元相关联的柱体。 这种装置中的至少一个可以包括被配置为在存储器单元之间存储信息到存储器单元中的模块和/或确定存储器单元中存储在存储单元中的信息的值。 该模块还可以被配置为向数据线和/或源施加具有正值的电压以控制身体的电位。 描述其他实施例。

    Memory device including voltage control for diffusion regions associated with memory blocks
    59.
    发明授权
    Memory device including voltage control for diffusion regions associated with memory blocks 有权

    公开(公告)号：US11664076B2

    公开(公告)日：2023-05-30

    申请号：US17217014

    申请日：2021-03-30

    Applicant: Micron Technology, Inc.

    Inventor： Go Shikata ,  Shigekazu Yamada

    IPC: G11C11/56 ,  G11C16/16 ,  G11C16/30

    CPC classification number: G11C16/16 ,  G11C16/30

    Abstract: Some embodiments include apparatuses and methods of operating the apparatuses. One of the apparatuses includes a first memory block including first word lines for respective first memory cells of the first memory block; a second memory block including second word lines for respective second memory cells of the second memory block; first diffusion regions coupled to the first word lines; second diffusion regions adjacent the first diffusion regions, the second diffusion regions coupled to the second word lines; and a circuit to apply a voltage to the second diffusion regions in a write operation performed on the first memory block.

    MEMORY DEVICE INCLUDING INITIAL CHARGING PHASE FOR DOUBLE SENSE OPERATION
    60.
    发明申请
    MEMORY DEVICE INCLUDING INITIAL CHARGING PHASE FOR DOUBLE SENSE OPERATION 有权

    公开(公告)号：US20230056107A1

    公开(公告)日：2023-02-23

    申请号：US17404204

    申请日：2021-08-17

    Applicant: Micron Technology, Inc.

    Inventor： Shigekazu Yamada

    IPC: G11C16/10 ,  G11C11/56 ,  G11C16/04 ,  G11C16/34

    Abstract: Some embodiments include apparatuses and methods using first and second data lines coupled to respective first and second memory cell strings; an access line shared by first and second memory cells of the first and second memory cell strings, respectively; and a control unit including circuitry to perform operations including charging the first data line to a first voltage during a first time interval of an operation performed on first and second memory cells; holding the second data line at a second voltage during the first time interval; charging the first data line to a third voltage during a second time interval of the operation; charging the second data line to a fourth voltage during the second time interval; and determining, during the second time interval of the operation, whether the first memory cell reaches a first threshold voltage and whether the second memory cell reaches a second threshold voltage.

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