公开(公告)号：US20240395325A1

公开(公告)日：2024-11-28

申请号：US18647354

申请日：2024-04-26

Applicant: Micron Technology, Inc.

Inventor： Shyam Surthi ,  James E. Davis ,  Kenneth W. Marr

IPC: G11C16/04 ,  H01L23/528 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35 ,  H10B99/00

Abstract: A semiconductor device including a substrate; a substrate; a memory array disposed on the substrate, the memory array including one or more memory planes, and a plurality of source region contact (SRC) nodes that are disposed on a backside surface of corresponding one of the one or more memory planes and above the substrate; a plurality of high-voltage (HV) diodes that are disposed in the substrate and that are connected to corresponding SRC nodes, the HV diodes including a first type dopant material; and a plurality of highly doped regions that are disposed in the substrate and that include a second type dopant material, each of the plurality of highly doped regions including a plurality of local maximum doping regions that are vertically aligned under a frontside surface of the substrate.

公开(公告)号：US20240170426A1

公开(公告)日：2024-05-23

申请号：US18383902

申请日：2023-10-26

Applicant: Micron Technology, Inc.

Inventor： Shyam Surthi ,  Onorato Di Cola

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/48 ,  H01L23/522 ,  H10B80/00

CPC classification number: H01L24/08 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L24/80 ,  H10B80/00 ,  H01L2224/08146 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: A semiconductor device assembly including a first module having one or more memory arrays, each of the one or more memory arrays being connected to a plurality of landing pads of the first module; and a second module having complementary metal-oxide-semiconductor devices, the second module including a plurality of socket shallow trench isolation (STI) regions disposed in a substrate of the second module, a plurality of metal routing layers connected to corresponding CMOS devices, a plurality of a first type of via contacts each being connected to a corresponding one of the plurality of metal routing layers, and a plurality of a second type of via contacts each being connected to a corresponding one of the plurality of landing pads of the first module, wherein the plurality of the first type of via contacts and the plurality of the second via contacts pass through the plurality of socket STI regions.

公开(公告)号：US11672120B2

公开(公告)日：2023-06-06

申请号：US17328237

申请日：2021-05-24

Applicant: Micron Technology, Inc.

Inventor： Byeung Chui Kim ,  Francois H. Fabreguette ,  Richard J. Hill ,  Purnima Narayanan ,  Shyam Surthi

IPC: H01L27/11582 ,  H01L21/02 ,  H01L27/1157 ,  G11C16/08

CPC classification number: H01L27/11582 ,  G11C16/08 ,  H01L21/0214 ,  H01L27/1157

Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and wordline levels. The wordline levels have conductive terminal ends within control gate regions. The control gate regions are vertically spaced from one another by first insulative regions which include first insulative material. Charge-storage material is laterally outward of the conductive terminal ends, and is configured as segments. The segments of the charge-storage material are arranged one atop another and are vertically spaced from one another by second insulative regions which include second insulative material. The second insulative material has a different dielectric constant than the first insulative material. Charge-tunneling material extends vertically along the stack, and is adjacent to the segments of the charge-trapping material. Channel material extends vertically along the stack, and is adjacent to the charge-tunneling material. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20230011076A1

公开(公告)日：2023-01-12

申请号：US17372891

申请日：2021-07-12

Applicant: Micron Technology, Inc.

Inventor： Shyam Surthi ,  Matthew Thorum

IPC: G11C16/04 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/532

Abstract: Some embodiments include an integrated assembly having a vertical stack of alternating first and second levels. A panel extends through the stack. The first levels have proximal regions adjacent the panel, and have distal regions further from the panel than the proximal regions. The distal regions include conductive structures. The conductive structures have a first thickness. The proximal regions include insulative structures. The insulative structures have a second thickness at least about as large as the first thickness. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11495610B2

公开(公告)日：2022-11-08

申请号：US16921641

申请日：2020-07-06

Applicant: Micron Technology, Inc.

Inventor： Collin Howder ,  Shyam Surthi ,  Matthew Thorum

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11524

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. The second tiers comprise doped silicon dioxide and the first tiers comprise a material other than doped silicon dioxide. The stack comprises laterally-spaced memory-block regions. Channel-material-string constructions extend through the first tiers and the second tiers in the memory-block regions. The doped silicon dioxide that is in the second tiers is etched selectively relative to said other material that is in the first tiers and selectively relative to and to expose an undoped silicon dioxide-comprising string of a charge-blocking material that is part of individual of the channel-material-string constructions. Structure independent of method is disclosed.

公开(公告)号：US11289501B2

公开(公告)日：2022-03-29

申请号：US16417162

申请日：2019-05-20

Applicant: Micron Technology, Inc.

Inventor： Shyam Surthi ,  Byeung Chul Kim ,  Richard J. Hill ,  Francois H. Fabreguette ,  Gurtej S. Sandhu

IPC: H01L27/11582 ,  G11C5/06 ,  H01L27/11565 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/1157

Abstract: Some embodiments include a memory array which has a vertical stack of alternating insulative levels and wordline levels. A channel material extends vertically along the stack. The channel material includes a semiconductor composition and has first segments alternating with second segments. The first segments are adjacent the wordline levels and the second segments are adjacent the insulative levels. The first segments have a first dopant distribution and the second segments have a second dopant distribution which is different from the first dopant distribution. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20220037357A1

公开(公告)日：2022-02-03

申请号：US17501951

申请日：2021-10-14

Applicant: Micron Technology, Inc.

Inventor： Byeung Chul Kim ,  Shyam Surthi

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157

Abstract: Some embodiments include a memory device having a vertical stack of alternating insulative levels and conductive levels. Memory cells are along the conductive levels. The conductive levels have control gate regions which include a first vertical thickness, have routing regions which include a second vertical thickness that is less than the first vertical thickness, and have tapered transition regions between the first vertical thickness and the second vertical thickness. Charge-blocking material is adjacent to the control gate regions. Charge-storage material is adjacent to the charge-blocking material. Dielectric material is adjacent to the charge-storage material. Channel material extends vertically along the vertical stack and is adjacent to the dielectric material. The memory cells include the control gate regions, and include regions of the charge-blocking material, the charge-storage material, the dielectric material and the channel material. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11171153B2

公开(公告)日：2021-11-09

申请号：US16681200

申请日：2019-11-12

Applicant: Micron Technology, Inc.

Inventor： Byeung Chul Kim ,  Shyam Surthi

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565

Abstract: Some embodiments include a memory device having a vertical stack of alternating insulative levels and conductive levels. Memory cells are along the conductive levels. The conductive levels have control gate regions which include a first vertical thickness, have routing regions which include a second vertical thickness that is less than the first vertical thickness, and have tapered transition regions between the first vertical thickness and the second vertical thickness. Charge-blocking material is adjacent to the control gate regions. Charge-storage material is adjacent to the charge-blocking material. Dielectric material is adjacent to the charge-storage material. Channel material extends vertically along the vertical stack and is adjacent to the dielectric material. The memory cells include the control gate regions, and include regions of the charge-blocking material, the charge-storage material, the dielectric material and the channel material. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20210343736A1

公开(公告)日：2021-11-04

申请号：US16862150

申请日：2020-04-29

Applicant: Micron Technology, Inc.

Inventor： Shyam Surthi ,  Chris M. Carlson ,  Richard J. Hill ,  Davide Resnati

IPC: H01L27/11556 ,  H01L27/06 ,  H01L27/11582 ,  G11C5/02

Abstract: An electronic structure comprising stacks comprising alternating dielectric materials and conductive materials in a cell region of the electronic structure. A pillar high-k dielectric material is adjacent to the stacks and in a pillar region of the electronic structure. A charge blocking material, a nitride material, a tunnel dielectric material, and a channel material are adjacent to the pillar high-k dielectric material in the pillar region of the electronic structure. A cell high-k dielectric material surrounds the conductive materials in the cell region of the electronic structure. The cell high-k dielectric material adjoins a portion of the pillar high-k dielectric material. Additional electronic structures are disclosed, as are related electronic devices, systems, and methods of forming an electronic device.

公开(公告)号：US20210343729A1

公开(公告)日：2021-11-04

申请号：US16863120

申请日：2020-04-30

Applicant: Micron Technology, Inc.

Inventor： Shyam Surthi ,  Richard J, Hill

IPC: H01L27/1157 ,  H01L27/11524 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582

Abstract: Some embodiments include an integrated assembly having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include conductive structures. Channel material extends vertically through the stack. The conductive structures have proximal regions near the channel material, and have distal regions further from the channel material than the proximal regions. The insulative levels have first regions vertically between the proximal regions of neighboring conductive structures, and have second regions vertically between the distal regions of the neighboring conductive structures. Voids are within the insulative levels and extend across portions of the first and second regions. Some embodiments include methods for forming integrated assemblies.