公开(公告)号：US11842078B2

公开(公告)日：2023-12-12

申请号：US17589080

申请日：2022-01-31

Applicant: Micron Technology, Inc.

Inventor： Andrea Giovanni Xotta ,  Guido Luciano Rizzo ,  Umberto Siciliani ,  Tommaso Vali ,  Luca De Santis ,  Walter Di Francesco

IPC: G06F12/00 ,  G06F3/06 ,  G06F9/48

CPC classification number: G06F3/0659 ,  G06F3/0619 ,  G06F3/0653 ,  G06F3/0679 ,  G06F9/4812

Abstract: A memory device includes a memory array configured with a plurality of memory planes, and control logic, operatively coupled with the memory array. The control logic performs a plurality of asynchronous memory access operations on the plurality of memory planes, detects an occurrence of an asynchronous interrupt event, and initiates a termination procedure for each of the plurality of asynchronous memory access operations to permit each of the plurality of asynchronous memory access operations to end at different times. In response to a first memory access operation of the plurality of asynchronous memory access operations ending, the control logic asserts a command result signal, wherein the command result signal is de-asserted automatically in response to receipt of a subsequent memory access command directed to any of the plurality of memory planes, and asserts a persistent event register signal, wherein the command result signal is de-asserted in response to receipt of a clear event register command.

公开(公告)号：US20230377626A1

公开(公告)日：2023-11-23

申请号：US17747183

申请日：2022-05-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yankang He ,  Walter Di Francesco ,  Luca Nubile ,  Chang Siau

IPC: G11C11/406 ,  G11C11/4072 ,  G11C11/4094

CPC classification number: G11C11/40611 ,  G11C11/40622 ,  G11C11/4072 ,  G11C11/4094

Abstract: One example of a memory device includes an array of flash memory cells, an array of Dynamic Random Access Memory (DRAM) memory cells, and a controller. The controller is configured to execute first instructions stored in the array of DRAM memory cells to access the array of flash memory cells.

公开(公告)号：US20230335200A1

公开(公告)日：2023-10-19

申请号：US18130589

申请日：2023-04-04

Applicant: Micron Technology, Inc.

Inventor： Chengbin Sun ,  Carmine Miccoli ,  Violante Moschiano ,  Srinath Venkatesan ,  Walter Di Francesco

IPC: G11C16/26 ,  G11C16/08 ,  G11C16/34

CPC classification number: G11C16/26 ,  G11C16/08 ,  G11C16/3404 ,  G11C2207/2254

Abstract: A memory device includes a memory array and control logic, operatively coupled to the memory array, to perform operations including causing a read operation to be initiated with respect to a set of target cells, determining whether the read operation has failed, in response to determining that the read operation has failed, obtaining, for each group of adjacent cells, respective cell state information, assigning, based on the cell state information, each target cell of the set of target cells to a respective state information bin of a set of state information bins, determining whether to initiate auto-calibrated corrective read, in response to determining to initiate auto-calibrated corrective read, performing read level offset calibration to determine a set of calibrated read level offsets, and causing the set of target cells to be read using the set of calibrated read level offsets.

公开(公告)号：US20230060312A1

公开(公告)日：2023-03-02

申请号：US17893364

申请日：2022-08-23

Applicant: Micron Technology, Inc.

Inventor： Violante Moschiano ,  Ali Mohammadzadeh ,  Walter Di Francesco ,  Dheeraj Srinivasan

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C7/10

Abstract: Described are systems and methods for implementing continuous memory programming operations. An example memory device comprises: a memory array comprising a plurality of memory cells electrically coupled to a plurality of conductive lines; and a controller coupled to the memory array. The controller performs operations comprising: performing a memory programming operation with respect to a set of memory cells of the memory array, wherein the memory programming operation comprises a sequence of programming pulses applied to one or more conductive lines electrically coupled to the set of memory cells; responsive to receiving a command to perform a memory access operation, suspending the memory programming operation after performing a current programming pulse of the sequence of programming pulses, wherein the current programming pulse is performed at a first voltage level; initiating the memory access operation; and resuming the memory programming operation by performing a next programming pulse at a second voltage level that exceeds the first voltage level.

公开(公告)号：US20220405013A1

公开(公告)日：2022-12-22

申请号：US17589080

申请日：2022-01-31

Applicant: Micron Technology, Inc.

Inventor： Andrea Giovanni Xotta ,  Guido Luciano Rizzo ,  Umberto Siciliani ,  Tommaso Vali ,  Luca De Santis ,  Walter Di Francesco

IPC: G06F3/06 ,  G06F9/48

Abstract: A memory device includes a memory array configured with a plurality of memory planes, and control logic, operatively coupled with the memory array. The control logic performs a plurality of asynchronous memory access operations on the plurality of memory planes, detects an occurrence of an asynchronous interrupt event, and initiates a termination procedure for each of the plurality of asynchronous memory access operations to permit each of the plurality of asynchronous memory access operations to end at different times. In response to a first memory access operation of the plurality of asynchronous memory access operations ending, the control logic asserts a command result signal, wherein the command result signal is de-asserted automatically in response to receipt of a subsequent memory access command directed to any of the plurality of memory planes, and asserts a persistent event register signal, wherein the command result signal is de-asserted in response to receipt of a clear event register command.

公开(公告)号：US11177014B1

公开(公告)日：2021-11-16

申请号：US17083138

申请日：2020-10-28

Applicant: Micron Technology, Inc.

Inventor： Violante Moschiano ,  Walter Di Francesco ,  Kishore Kumar Muchherla ,  Vamsi Pavan Rayaprolu ,  Jeffrey Scott McNeil, Jr.

IPC: G11C29/12 ,  G11C29/02 ,  G11C29/20 ,  G11C29/14

Abstract: A memory device to calibrate voltages used to read a group of memory cells. For example, the memory device measures first signal and noise characteristics of a group of memory cells by reading the group of memory cells at first test voltages that are separated from each other by a first voltage interval. An estimate of a read level of the group of memory cells is determined based on the first signal and noise characteristics. The memory device then measures second signal and noise characteristics of the group of memory cells by reading the group of memory cells at second test voltages that are separated from each other by a second voltage interval that is smaller than the first voltage interval. An optimized read voltage for the read level is computed from the second signal and noise characteristics.

公开(公告)号：US20210074374A1

公开(公告)日：2021-03-11

申请号：US17100582

申请日：2020-11-20

Applicant: Micron Technology, Inc.

Inventor： Michael G. Miller ,  Kishore Kumar Muchherla ,  Harish R. Singidi ,  Walter Di Francesco ,  Renato C. Padilla ,  Gary F. Besinga ,  Violante Moschiano

IPC: G11C16/34 ,  G06F12/02 ,  G11C29/52 ,  G11C29/50 ,  G11C16/04

Abstract: An indication of an initialization of power to a memory device is received. Responsive to receiving the indication of the initialization of power to the memory device, whether a status indicator associated with a written page of the memory device can be read is determined. Responsive to determining that the status indicator cannot be read, a programming of data to the memory device did not complete based on a prior loss of power to the memory device is determined.

公开(公告)号：US20200219573A1

公开(公告)日：2020-07-09

申请号：US16820636

申请日：2020-03-16

Applicant: Micron Technology, Inc.

Inventor： Michael G. Miller ,  Kishore Kumar Muchherla ,  Harish R. Singidi ,  Walter Di Francesco ,  Renato C. Padilla ,  Gary F. Besinga ,  Violante Moschiano

IPC: G11C16/34 ,  G11C29/50 ,  G06F12/02 ,  G11C16/04 ,  G11C29/52

Abstract: An indication of an initialization of power to a memory component can be received. In response to receiving the indication of the initialization, a last written page of a data block of the memory component can be identified. The last written page is associated with a status indicator. A determination is made of whether the status indicator is readable. Responsive to determining that the status indicator readable, it can be determined that programming of data to the data block of the memory component did complete and there is a data retention loss.

公开(公告)号：US20190018733A1

公开(公告)日：2019-01-17

申请号：US16105305

申请日：2018-08-20

Applicant: Micron Technology, Inc.

Inventor： Violante Moschiano ,  Walter Di Francesco ,  Luca De Santis ,  Giovanni Santin

IPC: G06F11/10 ,  G11C29/52 ,  H03M13/29

Abstract: A memory device includes a memory array that includes a buffer data. The memory device also includes a memory controller. The memory controller includes an error correction code (ECC) component. The memory controller further receives a status command and an indication related to the quality of the data to analyze with the ECC component. Based on a status value, the memory controller utilizes one of a plurality of error correction techniques via the ECC component to correct an error (e.g., soft state, calibration, etc.).

公开(公告)号：US20180210653A1

公开(公告)日：2018-07-26

申请号：US15532886

申请日：2017-01-23

Applicant: Micron Technology, Inc.

Inventor： Sivagnanam Parthasarathy ,  Terry M. Grunzke ,  Lucia Botticchio ,  Walter Di Francesco ,  Vamshi K. Indavarapu ,  Gianfranco Valeri ,  Renato C. Padilla ,  Ali Mohammadzadeh ,  Jung Sheng Hoei ,  Luca De Santis

IPC: G06F3/06 ,  G06F12/1009

CPC classification number: G06F3/064 ,  G06F3/0611 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/0246 ,  G06F12/1009 ,  G06F2212/1021 ,  G06F2212/2022 ,  G06F2212/7201

Abstract: The present disclosure relates to partially written block treatment. An example method comprises maintaining, internal to a memory device, a status of a last written page corresponding to a partially written block. Responsive to receiving, from a controller, a read request to a page of the partially written block, the example method can include determining, from page map information maintained internal to the memory device and from the status of the last written page, which of a number of different read trim sets to use to read the page of the partially written block corresponding to the read request.