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    Low power consumption type one-chip microcomputer having a plurality of peripheral circuits
    51.
    发明授权
    Low power consumption type one-chip microcomputer having a plurality of peripheral circuits 失效
    具有多个外围电路的低功耗型单片机

    公开(公告)号：US5511013A

    公开(公告)日：1996-04-23

    申请号：US274004

    申请日：1994-07-12

    申请人： Yusuke Tokieda ,  Hiroshi Katsuta

    发明人： Yusuke Tokieda ,  Hiroshi Katsuta

    IPC分类号： G06F1/04 ,  G06F1/32 ,  G06F15/78 ,  G06F1/00

    CPC分类号： G06F1/3215 ,  G06F1/325

    摘要： A microcomputer includes a plurality of peripheral circuits accessed by a central processing unit for a reading/writing of the peripheral circuits. Each of the external terminals supplies a selection signal indicative of use or non-use of a corresponding peripheral circuit. Each selection signal is supplied to a gate circuit provided for the corresponding peripheral circuit, for controlling permission and inhibition of application of a clock signal or a strobe signal to the corresponding peripheral circuit. Thus, neither the clock nor the strobe signal is supplied to the peripheral circuits which are not used in an actual application system, with the result that a low power consumption, highly reliable microcomputer is realized.

    摘要翻译： 微型计算机包括由中央处理单元访问的用于外围电路的读/写的多个外围电路。 每个外部端子提供指示使用或不使用相应的外围电路的选择信号。 每个选择信号被提供给为对应的外围电路提供的门电路，用于控制对相应的外围电路施加时钟信号或选通信号的许可和禁止。 因此，时钟和选通信号都不被提供给实际应用系统中未使用的外围电路，结果实现了低功耗，高可靠性的微计算机。

    Semiconductor device and support method for designing the same
    58.
    发明申请
    Semiconductor device and support method for designing the same 审中-公开
    半导体器件及其设计的支持方法

    公开(公告)号：US20070131647A1

    公开(公告)日：2007-06-14

    申请号：US11637035

    申请日：2006-12-12

    申请人： Hiroshi Katsuta

    发明人： Hiroshi Katsuta

    IPC分类号： C23F1/00

    CPC分类号： H01L27/0207 ,  G06F17/5068 ,  H01L27/11898

    摘要： A semiconductor device includes a bundle of wiring lines arranged in parallel and connected to a macro cell to transfer a same signal; and a bridge wiring line configured to bridge adjacent ones of the wiring lines of the bundle. Wiring line resistances between ends of the adjacent wiring lines in the macro cell and nodes of the bridge wiring line with the adjacent two wiring lines are different from each other.

    摘要翻译： 半导体器件包括并联布置并连接到宏单元以传输相同信号的一束布线; 以及桥接布线，其构造成桥接所述束的相邻布线。 在宏单元中的相邻布线的端部与相邻的两个布线的桥接布线的节点之间的布线电阻彼此不同。

    Arithmetic operation system for arithmetically operating a first operand having an actual point and a second operand having no actual point
    59.
    发明授权
    Arithmetic operation system for arithmetically operating a first operand having an actual point and a second operand having no actual point 失效
    用于算术运算具有实际点的第一操作数和没有实际点的第二操作数的算术运算系统

    公开(公告)号：US6014683A

    公开(公告)日：2000-01-11

    申请号：US995861

    申请日：1997-12-22

    申请人： Hiroshi Katsuta

    发明人： Hiroshi Katsuta

    IPC分类号： G06F7/38 ,  G06F7/48 ,  G06F7/483

    CPC分类号： G06F7/48 ,  G06F7/49936 ,  G06F7/49947

    摘要： An arithmetic operation system is provided, which is capable of floating-point arithmetic operation at high speed using minimal hardware devices. The position of an actual point of a first operand is detected by an actual point detector, resulting in a position data and a bit number data according to the detected position. A third operand having no actual point is generated by shifting the first operand having the actual point by the first shifter according to the bit number data. The second and third operands, both of which have no actual point, are arithmetically operated by an integer arithmetic operator to output a first operation result. The first operation result is rounded by a rounder according to the position data to output a second operation result. The second operation result having the actual position is generated by shifting the second operation result thus rounded to right by a second shifter according to the bit number data. Thus, the floating-point arithmetic operation for the first and second operands is able to be performed without any dedicated-purpose floating-point arithmetic processor nor operator.

    摘要翻译： 提供了一种算术运算系统，能够使用最小的硬件设备高速进行浮点算术运算。 第一操作数的实际点的位置由实际点检测器检测，导致根据检测到的位置的位置数据和位数数据。 通过根据比特数数据将具有实际点的第一操作数通过第一移位器移位来产生没有实际点的第三操作数。 这两个没有实际点的第二和第三操作数由整数算术运算符算术运算以输出第一运算结果。 第一操作结果根据位置数据由舍入器舍入，以输出第二操作结果。 具有实际位置的第二操作结果通过根据位数数据将第二移位器的第二操作结果向右舍入而产生。 因此，无需任何专用的浮点运算处理器和运算器就可以执行第一和第二操作数的浮点算术运算。

    Data processor having shared terminal for monitoring internal and external memory events
    60.
    发明授权
    Data processor having shared terminal for monitoring internal and external memory events 失效
    具有用于监视内部和外部存储器事件的共享终端的数据处理器

    公开(公告)号：US5771361A

    公开(公告)日：1998-06-23

    申请号：US490447

    申请日：1995-06-14

    申请人： Yusuke Tokieda ,  Hiroshi Katsuta

    发明人： Yusuke Tokieda ,  Hiroshi Katsuta

    IPC分类号： G06F11/28 ,  G06F11/36 ,  G06F15/78 ,  G06F13/00

    CPC分类号： G06F11/3656 ,  G06F11/364

    摘要： In a data processor, an internal memory stores instruction codes and a central processing unit reads an instruction code form the memory and produces an external access request if it contains an instruction to access an external memory which is connected to an external terminal. A bus controller is responsive to the request for producing a data timing signal and one of read and write signals. An external address bus and an external data bus are connected to the bus controller. An internal address bus is connected to the CPU for transporting an internal address signal. A selecting circuit is responsive to a first mode switching signal for coupling one of the external address bus and the external data bus to the external terminal and determining the direction of the data signal transported by the external data bus when it is coupled to the external terminal in accordance with the data timing signal and one of the read and write signals, and responsive to a second mode switching signal for coupling the internal address bus to the external terminal in the absence of the data timing signal and the read and write signals. For an external memory having separate data and address terminals, a second external terminal is additionally provided for coupling the external address bus direct to the address terminal of the external memory through the second external terminal, instead of through the selecting circuit.

    摘要翻译： 在数据处理器中，内部存储器存储指令代码，并且中央处理单元从存储器读取指令代码，并且如果其包含访问连接到外部端子的外部存储器的指令，则产生外部访问请求。 总线控制器响应于产生数据定时信号和读取和写入信号之一的请求。 外部地址总线和外部数据总线连接到总线控制器。 内部地址总线连接到CPU，用于传送内部地址信号。 选择电路响应于第一模式切换信号，用于将外部地址总线和外部数据总线中的一个耦合到外部端子，并且当外部数据总线耦合到外部端子时确定由外部数据总线传输的数据信号的方向 根据数据定时信号和读取和写入信号之一，并且响应于在不存在数据定时信号和读取和写入信号的情况下将内部地址总线耦合到外部端子的第二模式切换信号。 对于具有单独的数据和地址端子的外部存储器，另外提供第二外部端子，用于通过第二外部端子将外部地址总线直接耦合到外部存储器的地址端子，而不是通过选择电路。