公开(公告)号：US07330909B2

公开(公告)日：2008-02-12

申请号：US11519814

申请日：2006-09-13

申请人： Yasuo Inoue

发明人： Yasuo Inoue

IPC分类号： G06F3/00

CPC分类号： G06F3/0601 ,  G06F3/061 ,  G06F3/0656 ,  G06F3/0658 ,  G06F3/0689 ,  G06F12/0866 ,  G06F2003/0692 ,  G11C29/006 ,  H04L67/1097

摘要： A plurality of independent cache units and nonvolatile memory units are provided in a disk controller located between a host (central processing unit) and a magnetic disk drive. A plurality of channel units for controlling the data transfer to and from the central processing unit and a plurality of control units for controlling the data transfer to and from the magnetic disk drive are independently connected to the cache units and the nonvolatile memory units through data buses and access lines.

摘要翻译： 在位于主机（中央处理单元）和磁盘驱动器之间的盘控制器中提供多个独立高速缓存单元和非易失性存储器单元。 用于控制来自中央处理单元的数据传送的多个通道单元和用于控制与磁盘驱动器的数据传送的多个控制单元通过数据总线独立地连接到高速缓存单元和非易失性存储器单元 和接入线路。

公开(公告)号：US06383860B2

公开(公告)日：2002-05-07

申请号：US09908607

申请日：2001-07-20

申请人： Shigenobu Maeda ,  Yasuo Inoue ,  Hirotada Kuriyama ,  Shigeto Maegawa ,  Kyozo Kanamoto ,  Toshiaki Iwamatsu

发明人： Shigenobu Maeda ,  Yasuo Inoue ,  Hirotada Kuriyama ,  Shigeto Maegawa ,  Kyozo Kanamoto ,  Toshiaki Iwamatsu

IPC分类号： H01L218242

CPC分类号： H01L27/10823 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/10841 ,  H01L27/1203 ,  H01L29/78642

摘要： A first impurity diffusion layer forms one of source/drain regions and also forms a bit line. A first semiconductor layer, a channel semiconductor layer and a second semiconductor layer, which forms the other of source/drain regions and also forms a storage node, are disposed on the first impurity diffusion layer. A capacitor insulating film is disposed on a second conductive layer. A cell plate is disposed on a storage node with the capacitor insulating film therebetween. A capacitance of the bit line is reduced, and a dynamic random access memory thus constructed performs a high-speed operation.

摘要翻译： 第一杂质扩散层形成源极/漏极区之一并且还形成位线。 形成源极/漏极区域中的另一个并且还形成存储节点的第一半导体层，沟道半导体层和第二半导体层设置在第一杂质扩散层上。 电容绝缘膜设置在第二导电层上。 电池板设置在存储节点上，其间具有电容器绝缘膜。 位线的电容减小，并且由此构成的动态随机存取存储器执行高速操作。

公开(公告)号：US06341335B1

公开(公告)日：2002-01-22

申请号：US09181676

申请日：1998-10-29

申请人： Hiroki Kanai ,  Yasuo Inoue ,  Yoshifumi Takamoto

发明人： Hiroki Kanai ,  Yasuo Inoue ,  Yoshifumi Takamoto

IPC分类号： G06F1200

CPC分类号： G06F12/0862 ,  G06F9/383 ,  G06F12/0215 ,  G06F13/1631 ,  G06F2212/6022

摘要： An information processing system which reduces an access latency from a memory read request of a processor to a response thereto and also prevents reduction of the effective performance of a system bus caused by an increase in the access latency. In the information processing system, a memory controller is connected with the processor via a first bus and connected with a memory via a second bus, and a buffer memory is provided in the memory controller. The control circuit is controlled, before a memory access from the processor is carried out, to estimate an address to be possibly next accessed on the basis of addresses accessed in the past and to prefetch into the buffer memory, data stored in an address area continuous to the address and having a data size of twice or more an access unit of the processor.

摘要翻译： 一种信息处理系统，其将访问延迟从处理器的存储器读取请求减少到对其的响应，并且还防止由于访问等待时间的增加而导致的系统总线的有效性能的降低。 在信息处理系统中，存储器控制器经由第一总线与处理器连接，并经由第二总线与存储器连接，并且在存储器控制器中提供缓冲存储器。 在执行来自处理器的存储器访问之前，控制电路被控制以基于过去访问的地址来估计可能下一次被访问的地址并预取到缓冲存储器中，存储在连续的地址区域中的数据 并且具有处理器的访问单元的两倍或更多的数据大小。

公开(公告)号：US6127737A

公开(公告)日：2000-10-03

申请号：US943520

申请日：1997-10-03

申请人： Takashi Kuroi ,  Katsuyuki Horita ,  Maiko Sakai ,  Yasuo Inoue

发明人： Takashi Kuroi ,  Katsuyuki Horita ,  Maiko Sakai ,  Yasuo Inoue

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/8242 ,  H01L27/108 ,  H01L23/544

CPC分类号： H01L21/76232 ,  H01L21/76229

摘要： In a semiconductor device with a trench-type element isolation structure, alignment can be performed with high accuracy without any deterioration in device performance. The surfaces of silicon oxide films (2B, 2C) embedded in trenches (10B, 10C) of an element forming region including a memory cell region (11B) and a peripheral circuit region (11C) in a semiconductor substrate (1), respectively, are almost level with the surface of the semiconductor substrate (1). On the other hand, the surface of a silicon oxide film (2A) embedded in a trench (10A) is formed lower than the surface of the semiconductor substrate (1).

摘要翻译： 在具有沟槽型元件隔离结构的半导体器件中，可以高精度地进行对准，而不会使器件性能下降。 分别在半导体衬底（1）中嵌入包括存储单元区域（11B）的元件形成区域和外围电路区域（11C）的沟槽（10B，10C）中的氧化硅膜（2B，2C）的表面， 几乎与半导体衬底（1）的表面一致。 另一方面，嵌入在沟槽（10A）中的氧化硅膜（2A）的表面形成为低于半导体衬底（1）的表面。

公开(公告)号：US5841171A

公开(公告)日：1998-11-24

申请号：US746951

申请日：1996-11-18

申请人： Toshiaki Iwamatsu ,  Takashi Ipposhi ,  Yasuo Inoue

发明人： Toshiaki Iwamatsu ,  Takashi Ipposhi ,  Yasuo Inoue

IPC分类号： H01L21/316 ,  H01L21/76 ,  H01L21/762 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L29/00

CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/78609 ,  H01L29/78654

摘要： In forming an element isolating region in a silicon semiconductor layer of an SOI substrate, a silicon nitride film of a predetermined thickness is deposited over an oxide film formed on a SOI layer. The silicon nitride film is patterned in a design size of active regions, and side walls of a silicon nitride film are formed on the side surfaces of the patterned silicon nitride film. A first LOCOS process is carried out using the nitride film as an oxidation mask. A LOCOS film formed by the first LOCOS process is removed to form narrower concavities under the side walls. Then, another silicon nitride film is deposited, and is removed leaving portions thereof forming the concavities. Then, a second LOCOS process is carried out to form a LOCOS film as an element isolating region. The second LOCOS process uses the oxidation mask having the narrow cavities, so that stress at the boundary of the active region and the element isolation region is reduced, and the growth of bird's beaks can be suppressed.

摘要翻译： 在形成SOI衬底的硅半导体层中的元件隔离区域时，在形成于SOI层上的氧化物膜上沉积预定厚度的氮化硅膜。 以活性区域的设计尺寸对氮化硅膜进行构图，并且在图案化的氮化硅膜的侧表面上形成氮化硅膜的侧壁。 使用氮化物膜作为氧化掩模进行第一LOCOS工艺。 去除由第一LOCOS工艺形成的LOCOS膜，以在侧壁下形成更窄的凹面。 然后，沉积另一个氮化硅膜，并除去形成凹部的部分。 然后，进行第二LOCOS工艺以形成LOCOS膜作为元件隔离区。 第二LOCOS工艺使用具有窄腔的氧化掩模，使得有源区域和元件隔离区域的边界处的应力减小，并且可以抑制鸟喙的生长。

公开(公告)号：US5834288A

公开(公告)日：1998-11-10

申请号：US765491

申请日：1997-04-08

申请人： Yasuo Inoue ,  Sadako Inoue ,  Ken Kitajima

发明人： Yasuo Inoue ,  Sadako Inoue ,  Ken Kitajima

IPC分类号： C12N1/20 ,  C12N9/24 ,  C12P19/14 ,  C12R1/01 ,  C12N9/26

CPC分类号： C12Y302/01018 ,  C12N9/2402

摘要： The bacterium Sphingobacterium multivorum has been cultivated to produce a deaminoneuraminidase which is specific for catalyzing the hydrolysis of the ketosidic linkage formed by deaminoneuraminic acid in complex carbohydrates. The deaminoneuraminidase does not catalyze the hydrolysis of either the ketosidic linkage formed by N-acetylneuraminic acid or the ketosidic linkage formed by n-glycolylneuraminic acid and complex carbohydrates.

摘要翻译： PCT No.PCT / JP95 / 01213 Sec。 371日期1997年4月8日 102（e）日期1997年4月8日PCT Filed 1995年6月19日PCT Pub。 公开号WO96 / 00781 日期1996年1月11日已经培养了多细菌Sphingobacterium细菌以产生脱氨基神经氨酸酶，其对于催化由复合碳水化合物中的脱氨基神经氨酸形成的酮糖键的水解是特异性的。 脱氨基神经氨酸酶不催化由N-乙酰神经氨酸形成的酮糖键或由N-羟乙酰神经氨酸和复合碳水化合物形成的酮糖键的水解。

公开(公告)号：US5641980A

公开(公告)日：1997-06-24

申请号：US557558

申请日：1995-11-14

申请人： Yasuo Yamaguchi ,  Hans-Oliver Joachim ,  Yasuo Inoue

发明人： Yasuo Yamaguchi ,  Hans-Oliver Joachim ,  Yasuo Inoue

IPC分类号： H01L29/40 ,  H01L21/336 ,  H01L27/12 ,  H01L29/417 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/66757 ,  H01L27/1203 ,  H01L29/78606 ,  H01L29/78609 ,  H01L29/78621

摘要： It is an object to obtain a semiconductor device with the LDD structure having both operational stability and high speed and a manufacturing method thereof. A high concentration region (11) with boron of about 1.times.10.sup.18 /cm.sup.3 introduced therein is formed extending from under a channel formation region (4) to under a drain region (6) and a source region (6') in a silicon substrate (1). The high concentration region (11) is formed in the surface of the silicon substrate (1) under the channel formation region (4), and is formed at a predetermined depth from the surface of the silicon substrate (1) under the drain region (6) and the source region (6'). A low concentration region (10) is formed in the surface of the silicon substrate (1) under the drain region (6) and the source region (6'). The formation of the high concentration region only in the surface of the semiconductor substrate under the channel formation region surely suppresses an increase in the leakage current and an increase in the drain capacitance.

摘要翻译： 本发明的目的是获得具有操作稳定性和高速度的LDD结构的半导体器件及其制造方法。 导入其中引入了约1×10 18 / cm 3的硼的高浓度区域（11）形成在沟道形成区域（4）下方延伸到漏极区域（6）下方的硅衬底（1）中的源极区域（6'） ）。 在硅衬底（1）的沟道形成区域（4）的表面上形成高浓度区域（11），并且形成在与硅衬底（1）的漏极区域 6）和源极区（6'）。 在漏极区域（6）和源极区域（6'）的下方的硅衬底（1）的表面中形成低浓度区域（10）。 仅在沟道形成区域的半导体衬底的表面形成高浓度区域确实地抑制了漏电流的增加和漏极电容的增加。

公开(公告)号：US5640600A

公开(公告)日：1997-06-17

申请号：US381560

申请日：1995-01-31

申请人： Takao Satoh ,  Hisaharu Takeuchi ,  Yasuo Inoue ,  Akira Yamamoto

发明人： Takao Satoh ,  Hisaharu Takeuchi ,  Yasuo Inoue ,  Akira Yamamoto

IPC分类号： G06F13/16 ,  G06F3/06 ,  G06F11/34 ,  G06F13/12 ,  G06F13/36 ,  H01J3/00

CPC分类号： G06F13/124 ,  G06F11/349 ,  G06F11/3409 ,  G06F2201/88 ,  G06F2201/885

摘要： A storage controller comprising a storage device adapter, a channel adapter, a cache memory, a control memory, and a plurality of buses connecting therebetween. The channel adapter communicates with a processor and processes input/output requests issued by the processor. The storage device adapter controls a storage device and data transfer between the storage device and the cache memory. The channel adapter and the storage device adapter exchanges control information via the control memory. The buses are used to transfer the data and the control information between the cache memory and the control memory, and the channel adapter and the storage device adapter. The controller also comprises bus load estimating means and bus mode selecting means. The bus load estimating means estimates bus load characteristics as an index based on the amount of data transfer during sequential access to the storage device. The bus mode selecting means determines a bus mode of bus utilization based on the index. Each of the channel adapter and the storage device adapter has bus access means for accessing the buses in accordance with the bus mode selected by the bus mode selecting means.

摘要翻译： 存储控制器，包括存储设备适配器，信道适配器，高速缓冲存储器，控制存储器以及连接在它们之间的多个总线。 信道适配器与处理器通信并处理由处理器发出的输入/输出请求。 存储设备适配器控制存储设备和存储设备与高速缓冲存储器之间的数据传输。 通道适配器和存储设备适配器通过控制存储器交换控制信息。 总线用于将数据和控制信息传输到缓存存储器和控制存储器之间，以及通道适配器和存储设备适配器。 控制器还包括总线负载估计装置和总线模式选择装置。 总线负载估计装置基于在顺序访问存储设备期间的数据传输量来估计总线负载特性作为索引。 总线模式选择装置根据该索引确定总线利用的总线模式。 每个通道适配器和存储设备适配器具有总线访问装置，用于根据由总线模式选择装置选择的总线模式访问总线。

公开(公告)号：US5459856A

公开(公告)日：1995-10-17

申请号：US984763

申请日：1992-12-03

申请人： Yasuo Inoue

发明人： Yasuo Inoue

IPC分类号： G06F3/06 ,  G06F3/00 ,  G06F12/08 ,  G06F13/12 ,  G06F13/14 ,  G06F13/38 ,  G11C29/00 ,  G06F11/20

CPC分类号： G06F3/0601 ,  G06F12/0866 ,  G06F3/061 ,  G06F3/0656 ,  G06F3/0658 ,  G06F3/0689 ,  G11C29/006 ,  H04L67/1097 ,  G06F2003/0692

摘要： A plurality of independent cache units and nonvolatile memory units are provided in a disk controller located between a host (central processing unit) and a magnetic disk drive. A plurality of channel units for controlling the data transfer to and from the central processing unit and a plurality of control units for controlling the data transfer to and from the magnetic disk drive are independently connected to the cache units and the nonvolatile memory units through data buses and access lines.

摘要翻译： 在位于主机（中央处理单元）和磁盘驱动器之间的盘控制器中提供多个独立高速缓存单元和非易失性存储器单元。 用于控制来自中央处理单元的数据传送的多个通道单元和用于控制与磁盘驱动器的数据传送的多个控制单元通过数据总线独立地连接到高速缓存单元和非易失性存储器单元 和接入线路。

公开(公告)号：US5340645A

公开(公告)日：1994-08-23

申请号：US24832

申请日：1993-03-02

申请人： Hidefumi Harada ,  Yasuo Inoue

发明人： Hidefumi Harada ,  Yasuo Inoue

IPC分类号： C01G23/00 ,  C08K7/00 ,  C08K7/08 ,  C08L101/00 ,  C22C47/00 ,  C22C49/00 ,  C22C49/04 ,  C22C49/06 ,  D01F9/08 ,  B32B5/02 ,  C04B35/02

CPC分类号： D01F9/08 ,  C01G23/005 ,  C01P2004/10 ,  C01P2004/61 ,  C01P2006/60 ,  Y10T428/24994 ,  Y10T428/249948 ,  Y10T428/294 ,  Y10T428/2975 ,  Y10T428/31507 ,  Y10T428/31678

摘要： Potassium hexatitanate fibers having a tunnel structure and a free potassium content of 5 ppm or less can be produced by mixing together a titanium containing compound and a potassium containing compound in a ratio represented by the formula K.sub.2 O.nTiO.sub.2 (wherein n=from 2 to 4); firing the mixture at 900.degree. to 1,200.degree. C. to produce mass of potassium titanate fibers; dipping the mass of product in either cold or hot water to disintegrate the mass of potassium titanate fibers into individual single fibers; adding an acid to the slurry to adjust the pH value to 9.3-9.7, thereby changing the composition of the potassium titanate fibers so that the molar ratio of TiO.sub.2 /K.sub.2 O is in the range of from 5.95 to 6.00; heating the fibers at 950.degree. to 1,150.degree. C. for 1 hour or more; and washing the fibers with an acid. The potassium hexatitanate fibers, which have a minimal free potassium content, i.e., 5 ppm or less, can be suitably used as a reinforcing material for polyester thermoplastic resins, polyphenylene sulfide resins, liquid crystal polymers, aluminum alloys, magnesium alloys and so forth, all of which are easily affected by free potassium.

摘要翻译： 通过将含钛化合物和含钾化合物以通式K 2 O·nTiO 2（其中n = 2〜4）表示的比例混合在一起，可以制备具有隧道结构和游离钾含量为5ppm以下的六钛酸钾纤维 ）; 在900〜1200℃下烧成混合物，生成钛酸钾纤维; 将产品的质量浸入冷或热水中以将钛酸钾纤维的质量分解成单个单根纤维; 向浆料中加入酸以将pH值调节至9.3-9.7，从而改变钛酸钾纤维的组成，使得TiO 2 / K 2 O的摩尔比在5.95至6.00的范围内; 在950〜1150℃下加热纤维1小时以上; 并用酸洗涤纤维。 具有最小游离钾含量（即5ppm以下）的六钛酸钾纤维可以适合用作聚酯热塑性树脂，聚苯硫醚树脂，液晶聚合物，铝合金，镁合金等的增强材料， 所有这些都容易受到游离钾的影响。