公开(公告)号：US12057482B2

公开(公告)日：2024-08-06

申请号：US17395239

申请日：2021-08-05

Applicant: MaxPower Semiconductor, Inc.

Inventor： Jun Zeng ,  Mohamed N. Darwish ,  Shih-Tzung Su

IPC: H01L29/423 ,  H01L23/60 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/4236 ,  H01L23/60 ,  H01L29/66719 ,  H01L29/66734 ,  H01L29/7813

Abstract: A vertical trench MOSFET is formed with deep P-shield regions below portions of each gate trench. The deep P-shield regions are effectively downward extensions of the P-body/well, and are electrically coupled to the top source electrode. The P-shield regions abut the bottom portions and lower sides of the gate trenches, so that those small portions of the gate trench do not create N-channels and do not conduct current. Accordingly, each trench comprises an active gate portion that creates an N-channel and a small non-active portion that abuts the P-shield regions. The spacing of the P-shield regions along each gate trench is selected to achieve the desired electric field spreading to protect the gate oxide from punch-through. No field plate trenches are needed to be formed in the active area of the MOSFET. The deep P-shield regions are formed by implanting P-type dopants through the bottom of the trenches.

公开(公告)号：US20210175348A1

公开(公告)日：2021-06-10

申请号：US16933890

申请日：2020-07-20

Applicant: MaxPower Semiconductor Inc.

Inventor： Mohamed N. Darwish ,  Jun Zeng ,  Richard A. Blanchard

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/417 ,  H01L29/40 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L21/265 ,  H01L21/8234 ,  H01L29/36 ,  H01L29/423 ,  H01L29/739

Abstract: Methods and systems for power semiconductor devices integrating multiple quasi-vertical transistors on a single chip. Multiple power transistors (or active regions) are paralleled, but one transistor has a lower threshold voltage. This reduces the voltage drop when the transistor is forward-biased. In an alternative embodiment, the power device with lower threshold voltage is simply connected as a depletion diode, to thereby shunt the body diodes of the active transistors, without affecting turn-on and ON-state behavior.

公开(公告)号：US20200279926A1

公开(公告)日：2020-09-03

申请号：US16704384

申请日：2019-12-05

Applicant: MaxPower Semiconductor Inc.

Inventor： Mohamed N. Darwish ,  Jun Zeng ,  Hamza Yilmaz ,  Richard A. Blanchard

IPC: H01L29/40 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78

Abstract: Methods and systems for lateral power devices, and methods for operating them, in which charge balancing is implemented in a new way. In a first inventive teaching, the lateral conduction path is laterally flanked by regions of opposite conductivity type which are self-aligned to isolation trenches which define the surface geometry of the channel. In a second inventive teaching, which can be used separately or in synergistic combination with the first teaching, the drain regions are self-isolated. In a third inventive teaching, which can be used in synergistic combination with the first and/or second teachings, the source regions are also isolated from each other. In a fourth inventive teaching, the lateral conduction path is also overlain by an additional region of opposite conductivity type.

公开(公告)号：US20200273987A1

公开(公告)日：2020-08-27

申请号：US16782996

申请日：2020-02-05

Applicant: MaxPower Semiconductor Inc.

Inventor： Jun Zeng ,  Kui Pu ,  Mohamed N. Darwish ,  Shih-Tzung Su

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/66 ,  H01L29/08 ,  H01L29/417

Abstract: A split gate power device is disclosed having a trench containing a U-shaped gate that, when biased above a threshold voltage, creates a conductive channel in a p-well. Below the gate is a field plate in the trench, coupled to the source electrode, for spreading the electric field along the trench to improve the breakdown voltage. The top gate poly is initially formed relatively thin so that it can be patterned using non-CMP techniques, such as dry etching or wet etching. As such, the power device can be fabricated in conventional fabs not having CMP capability. In one embodiment, the thin gate has vertical and lateral portions that create conductive vertical and lateral channels in a p-well. In another embodiment, the thin gate has only vertical portions along the trench sidewalls for minimizing surface area and gate capacitance.

公开(公告)号：US10529810B1

公开(公告)日：2020-01-07

申请号：US15374875

申请日：2016-12-09

Applicant: MaxPower Semiconductor Inc.

Inventor： Mohamed N. Darwish ,  Jun Zeng ,  Hamza Yilmaz ,  Richard A. Blanchard

IPC: H01L29/40 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10

Abstract: Methods and systems for lateral power devices, and methods for operating them, in which charge balancing is implemented in a new way. In a first inventive teaching, the lateral conduction path is laterally flanked by regions of opposite conductivity type which are self-aligned to isolation trenches which define the surface geometry of the channel. In a second inventive teaching, which can be used separately or in synergistic combination with the first teaching, the drain regions are self-isolated. In a third inventive teaching, which can be used in synergistic combination with the first and/or second teachings, the source regions are also isolated from each other. In a fourth inventive teaching, the lateral conduction path is also overlain by an additional region of opposite conductivity type.

公开(公告)号：US20200006499A1

公开(公告)日：2020-01-02

申请号：US15374875

申请日：2016-12-09

Applicant: MaxPower Semiconductor Inc.

Inventor： Mohamed N. Darwish ,  Jun Zeng ,  Hamza Yilmaz ,  Richard A. Blanchard

IPC: H01L29/40 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10

Abstract: Methods and systems for lateral power devices, and methods for operating them, in which charge balancing is implemented in a new way. In a first inventive teaching, the lateral conduction path is laterally flanked by regions of opposite conductivity type which are self-aligned to isolation trenches which define the surface geometry of the channel. In a second inventive teaching, which can be used separately or in synergistic combination with the first teaching, the drain regions are self-isolated. In a third inventive teaching, which can be used in synergistic combination with the first and/or second teachings, the source regions are also isolated from each other. In a fourth inventive teaching, the lateral conduction path is also overlain by an additional region of opposite conductivity type.

公开(公告)号：US20190097025A1

公开(公告)日：2019-03-28

申请号：US16148578

申请日：2018-10-01

Applicant: MaxPower Semiconductor Inc.

Inventor： Mohamed N. Darwish ,  Jun Zeng ,  Richard A. Blanchard

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/739 ,  H01L29/423 ,  H01L29/40 ,  H01L29/417 ,  H01L29/16 ,  H01L29/08 ,  H01L29/10 ,  H01L21/265 ,  H01L29/36 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L29/66734 ,  H01L21/26506 ,  H01L21/823412 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1033 ,  H01L29/1095 ,  H01L29/16 ,  H01L29/36 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66666 ,  H01L29/66727 ,  H01L29/7395 ,  H01L29/7803 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/7831 ,  H01L29/7835

Abstract: Methods and systems for power semiconductor devices integrating multiple trench transistors on a single chip. Multiple power transistors (or active regions) are paralleled, but one transistor has a lower threshold voltage. This reduces the voltage drop when the transistor is forward-biased. In an alternative embodiment, the power device with lower threshold voltage is simply connected as a depletion diode, to thereby shunt the body diodes of the active transistors, without affecting turn-on and ON-state behavior.

公开(公告)号：US20180366569A1

公开(公告)日：2018-12-20

申请号：US16006693

申请日：2018-06-12

Applicant: MaxPower Semiconductor Inc.

Inventor： Jun Zeng ,  Mohamed N. Darwish

IPC: H01L29/778 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/40 ,  H01L29/16 ,  H01L29/165 ,  H01L29/66 ,  H01L21/324 ,  H01L21/02 ,  H01L21/28 ,  H01L29/267 ,  H01L29/739

Abstract: Heterostructure and double-heterostructure trench-gate devices, in which the substrate and/or the body are constructed of a narrower-bandgap semiconductor material than the uppermost portion of the drift region. Fabrication most preferably uses a process where gate dielectric anneal is performed after all other high-temperature steps have already been done.

公开(公告)号：US09997614B2

公开(公告)日：2018-06-12

申请号：US14694929

申请日：2015-04-23

Applicant: MaxPower Semiconductor Inc.

Inventor： Mohamed N. Darwish ,  Jun Zeng ,  Richard A. Blanchard

IPC: H01L29/66 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L27/088 ,  H01L29/40 ,  H01L29/10 ,  H01L21/265 ,  H01L21/8234 ,  H01L29/16 ,  H01L29/36 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L29/66734 ,  H01L21/26506 ,  H01L21/823412 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1033 ,  H01L29/1095 ,  H01L29/16 ,  H01L29/36 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66666 ,  H01L29/66727 ,  H01L29/7395 ,  H01L29/7803 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/7831 ,  H01L29/7835

Abstract: Methods and systems for power semiconductor devices integrating multiple quasi-vertical transistors on a single chip. Multiple power transistors (or active regions) are paralleled, but one transistor has a lower threshold voltage. This reduces the voltage drop when the transistor is forward-biased. In an alternative embodiment, the power device with lower threshold voltage is simply connected as a depletion diode, to thereby shunt the body diodes of the active transistors, without affecting turn-on and ON-state behavior.

公开(公告)号：US09923556B2

公开(公告)日：2018-03-20

申请号：US15182558

申请日：2016-06-14

Applicant: MaxPower Semiconductor Inc.

Inventor： Mohamed N. Darwish ,  Jun Zeng

IPC: H01L29/78 ,  H03K17/041 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/786 ,  H01L21/265

CPC classification number: H01L29/7816 ,  H01L21/26586 ,  H01L29/0619 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0661 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/408 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66734 ,  H01L29/7802 ,  H01L29/7809 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/7835 ,  H01L29/78624 ,  H03K17/04106

Abstract: Lateral power devices where immobile electrostatic charge is emplaced in dielectric material adjoining the drift region. A shield gate is interposed between the gate electrode and the drain, to reduce the Miller charge. In some embodiments the gate electrode is a trench gate, and in such cases the shield electrode too is preferably vertically extended.