公开(公告)号：US20210287990A1

公开(公告)日：2021-09-16

申请号：US16820046

申请日：2020-03-16

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Christian George Emor ,  Luca Fumagalli ,  John D. Hopkins ,  Rita J. Klein ,  Christopher W. Petz ,  Everett A. McTeer

IPC: H01L23/535 ,  H01L23/532 ,  H01L21/768 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582

Abstract: A microelectronic device comprises a first conductive structure, a barrier structure, a conductive liner structure, and a second conductive structure. The first conductive structure is within a first filled opening in a first dielectric structure. The barrier structure is within the first filled opening in the first dielectric structure and vertically overlies the first conductive structure. The conductive liner structure is on the barrier structure and is within a second filled opening in a second dielectric structure vertically overlying the first dielectric structure. The second conductive structure vertically overlies and is horizontally surrounded by the conductive liner structure within the second filled opening in the second dielectric structure. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.

公开(公告)号：US20210287989A1

公开(公告)日：2021-09-16

申请号：US16817267

申请日：2020-03-12

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  John D. Hopkins ,  Rita J. Klein ,  Everett A. McTeer ,  Lifang Xu ,  Daniel Billingsley ,  Collin Howder

IPC: H01L23/535 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

Abstract: A microelectronic device comprises a stack structure, a staircase structure, conductive pad structures, and conductive contact structures. The stack structure comprises vertically alternating conductive structures and insulating structures arranged in tiers. Each of the tiers individually comprises one of the conductive structures and one of the insulating structures. The staircase structure has steps comprising edges of at least some of the tiers of the stack structure. The conductive pad structures are on the steps of the staircase structure and comprise beta phase tungsten. The conductive contact structures are on the conductive pad structures. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.

公开(公告)号：US20210265171A1

公开(公告)日：2021-08-26

申请号：US17318470

申请日：2021-05-12

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Gordon A. Haller ,  Tom J. John ,  Anish A. Khandekar ,  Christopher Larsen ,  Kunal Shrotri

IPC: H01L21/311 ,  H01L27/11556 ,  H01L21/02 ,  H01L27/11582

Abstract: A method used in forming an array of elevationally-extending strings of memory cells comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. The stack comprises an etch-stop tier between a first tier and a second tier of the stack. The etch-stop tier is of different composition from those of the insulative tiers and the wordline tiers. Etching is conducted into the insulative tiers and the wordline tiers that are above the etch-stop tier to the etch-stop tier to form channel openings that have individual bases comprising the etch-stop tier. The etch-stop tier is penetrated through to extend individual of the channel openings there-through. After extending the individual channel openings through the etch-stop tier, etching is conducted into and through the insulative tiers and the wordline tiers that are below the etch-stop tier to extend the individual channel openings deeper into the stack below the etch-stop tier. Transistor channel material is formed in the individual channel openings elevationally along the etch-stop tier and along the insulative tiers and the wordline tiers that are above and below the etch-stop tier. Arrays independent of method are disclosed.

公开(公告)号：US20210249261A1

公开(公告)日：2021-08-12

申请号：US16789168

申请日：2020-02-12

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Damir Fazil

IPC: H01L21/02 ,  H01L21/311

Abstract: A method of forming a microelectronic device comprises forming openings in an interdeck region and a first deck structure, the first deck structure comprising alternating levels of a first insulative material and a second insulative material, forming a first sacrificial material in the openings, removing a portion of the first sacrificial material from the interdeck region to expose sidewalls of the first insulative material and the second insulative material in the interdeck region, removing a portion of the first insulative material and the second insulative material in the interdeck region to form tapered sidewalls in the interdeck region, removing remaining portions of the first sacrificial material from the openings, and forming at least a second sacrificial material in the openings. Related methods of forming a microelectronic devices and related microelectronic devices are disclosed.

公开(公告)号：US11056505B2

公开(公告)日：2021-07-06

申请号：US16708673

申请日：2019-12-10

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Purnima Narayanan ,  Jordan D. Greenlee

IPC: H01L27/115 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L23/522 ,  H01L21/768 ,  H01L21/3215 ,  H01L21/311 ,  H01L27/11578 ,  H01L27/06

Abstract: Some embodiments include a method of forming an integrated assembly. A stack of alternating first and second materials is formed over a conductive structure. The conductive structure includes a semiconductor-containing material over a metal-containing material. An opening is formed to extend through the stack and through the semiconductor-containing material, to expose the metal-containing material. The semiconductor-containing material is doped with carbon and/or with one or more metals. After the doping of the semiconductor-containing material, the second material of the stack is removed to form voids. Conductive material is formed within the voids. Insulative material is formed within the opening. Some embodiments include integrated assemblies having carbon distributed within at least a portion of a semiconductor material.

公开(公告)号：US20210202324A1

公开(公告)日：2021-07-01

申请号：US16728962

申请日：2019-12-27

Applicant: Micron Technology, Inc.

Inventor： Alyssa N. Scarbrough ,  John D. Hopkins

IPC: H01L21/8234 ,  H01L27/11556 ,  H01L27/11582

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. The stack comprises laterally-spaced memory-block regions that have horizontally-elongated trenches there-between. Sacrificial material is formed in the trenches. Vertical recesses are formed in the sacrificial material. The vertical recesses extend across the trenches laterally-between and are longitudinally-spaced-along immediately-laterally-adjacent of the memory-block regions. Bridge material is formed in the vertical recesses to line and less-than-fill the vertical recesses and form bridges there-from that have an upwardly-open cup-like shape. The sacrificial material in the trenches is replaced with intervening material that is directly under the bridges. Additional methods and structures independent of methods are disclosed.

公开(公告)号：US11049768B2

公开(公告)日：2021-06-29

申请号：US16667733

申请日：2019-10-29

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Jiewei Chen ,  Nancy M. Lomeli

IPC: H01L21/4763 ,  H01L21/768 ,  H01L27/11582 ,  G11C5/02 ,  H01L27/11556

Abstract: A method of forming a microelectronic device comprises forming a stack structure comprising insulative structures and additional insulative structures vertically alternating with the insulative structures. Apertures are formed to extend to surfaces of the insulative structures at different depths than one another within the stack structure. Dielectric liner structures are formed within the apertures. Sacrificial structures are formed within portions of the apertures remaining unoccupied by the dielectric liner structures. Upper portions of the sacrificial structures are replaced with capping structures. Portions of the insulative structures and remaining portions of the sacrificial structures are replaced with electrically conductive material. Microelectronic devices and electronic systems are also described.

公开(公告)号：US11024644B2

公开(公告)日：2021-06-01

申请号：US16548471

申请日：2019-08-22

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Shyam Surthi ,  Jordan D. Greenlee

IPC: H01L27/11582 ,  H01L29/49 ,  H01L29/51 ,  H01L21/28 ,  H01L29/792 ,  H01L29/788 ,  H01L21/02 ,  H01L27/11556

Abstract: Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include terminal regions, and include nonterminal regions proximate the terminal regions. The terminal regions are vertically thicker than the nonterminal regions, and are configured as segments which are vertically stacked one atop another and which are vertically spaced from one another. Blocks are adjacent to the segments and have approximately a same vertical thickness as the segments. The blocks include high-k dielectric material, charge-blocking material and charge-storage material. Channel material extends vertically along the stack and is adjacent to the blocks. Some embodiments include integrated assemblies. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US10943920B2

公开(公告)日：2021-03-09

申请号：US16738499

申请日：2020-01-09

Applicant: Micron Technology, Inc.

Inventor： John M. Meldrim ,  Yushi Hu ,  Rita J. Klein ,  John D. Hopkins ,  Hongbin Zhu ,  Gordon A. Haller ,  Luan C. Tran

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L21/28 ,  H01L29/49

Abstract: Some embodiments include a memory array which has a stack of alternating first and second levels. Channel material pillars extend through the stack, and vertically-stacked memory cell strings are along the channel material pillars. A common source is under the stack and electrically coupled to the channel material pillars. The common source has conductive protective material over and directly against metal silicide, with the conductive protective material being a composition other than metal silicide. Some embodiments include methods of fabricating integrated structures.

公开(公告)号：US20200258910A1

公开(公告)日：2020-08-13

申请号：US16861093

申请日：2020-04-28

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Meng-Wei Kuo ,  John D. Hopkins

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11524 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/311 ,  H01L27/11556

Abstract: Some embodiments include a method of forming vertically-stacked memory cells. An opening is formed through a stack of alternating insulative and conductive levels. Cavities are formed to extend into the conductive levels. Regions of the insulative levels remain as ledges which separate adjacent cavities from one another. Material is removed from the ledges to thin the ledges, and then charge-blocking dielectric and charge-storage structures are formed within the cavities. Some embodiments include an integrated structure having a stack of alternating insulative levels and conductive levels. Cavities extend into the conductive levels. Ledges of the insulative levels separate adjacent cavities from one another. The ledges are thinned relative to regions of the insulative levels not encompassed by the ledges. Charge-blocking dielectric and charge-storage structures are within the cavities.