公开(公告)号：US12190947B2

公开(公告)日：2025-01-07

申请号：US17562598

申请日：2021-12-27

Applicant: Micron Technology, Inc.

Inventor： Jonathan J. Strand ,  Sukneet Singh Basuta ,  Shashank Bangalore Lakshman ,  Jonathan D. Harms

IPC: G11C11/56 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  G11C29/50

Abstract: Methods, systems, and devices for imprint recovery for memory arrays are described. In some cases, memory cells may become imprinted, which may refer to conditions where a cell becomes predisposed toward storing one logic state over another, resistant to being written to a different logic state, or both. Imprinted memory cells may be recovered using a recovery or repair process that may be initiated according to various conditions, detections, or inferences. In some examples, a system may be configured to perform imprint recovery operations that are scaled or selected according to a characterized severity of imprint, an operational mode, environmental conditions, and other factors. Imprint management techniques may increase the robustness, accuracy, or efficiency with which a memory system, or components thereof, can operate in the presence of conditions associated with memory cell imprinting.

公开(公告)号：US20240421999A1

公开(公告)日：2024-12-19

申请号：US18817096

申请日：2024-08-27

Applicant: Micron Technology, Inc.

Inventor： Jonathan D. Harms

IPC: H04L9/32 ,  G06Q20/06 ,  G06Q20/38 ,  H04L9/00

Abstract: Computerized apparatus using characterized devices such as memories for intensive computational applications such as blockchain processing. In one embodiment, the computerized apparatus comprises a computational appliance (e.g., stand-alone box, server blade, plug-in card, or mobile device) that includes characterized memory devices. These memory devices are associated with a range of performances over a range of operational parameters, and can be used in conjunction with a solution density function to optimize memory searching. In one embodiment, the ledger appliance can communicate with other ledger appliances to create and/or use a blockchain ledger so as to facilitate decentralized exchanges between untrusted parties. In some variants, the ledger appliance may additionally use an application programming interface (API) to dynamically generate blockchains on the fly. Various other applications are also described (e.g., social media, machine learning, probabilistic applications and other error-tolerant applications).

公开(公告)号：US12040038B2

公开(公告)日：2024-07-16

申请号：US18084892

申请日：2022-12-20

Applicant: Micron Technology, Inc.

Inventor： Jonathan D. Harms ,  Jonathan J. Strand ,  Sukneet Singh Basuta ,  Shashank Bangalore Lakshman

IPC: G11C11/22 ,  G11C29/50

CPC classification number: G11C29/50004 ,  G11C11/221 ,  G11C11/2259 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/2293 ,  G11C2029/5004

Abstract: Methods, systems, and devices for imprint recovery for memory cells are described. In some cases, memory cells may become imprinted, which may refer to conditions where a cell becomes predisposed toward storing one logic state over another, resistant to being written to a different logic state, or both. Imprinted memory cells may be recovered using a recovery or repair process that may be initiated according to various conditions, detections, or inferences. In some examples, a system may be configured to perform imprint recovery operations that are scaled or selected according to a characterized severity of imprint, an operational mode, environmental conditions, and other factors. Imprint management techniques may increase the robustness, accuracy, or efficiency with which a memory system, or components thereof, can operate in the presence of conditions associated with memory cell imprinting.

公开(公告)号：US11954499B2

公开(公告)日：2024-04-09

申请号：US17885143

申请日：2022-08-10

Applicant: Micron Technology, Inc.

Inventor： Troy A. Manning ,  Jonathan D. Harms ,  Troy D. Larsen ,  Glen E. Hush ,  Timothy P. Finkbeiner

IPC: G06F9/4401 ,  G06F9/38 ,  G06F12/0868 ,  G06F12/1045 ,  G06F13/16

CPC classification number: G06F9/4403 ,  G06F9/3836 ,  G06F9/4406 ,  G06F12/0868 ,  G06F12/1054 ,  G06F13/1668 ,  G06F2212/7201 ,  G06F2212/7211

Abstract: Methods, systems, and devices for operational code storage for an on-die microprocessor are described. A microprocessor may be formed on-die with a memory array. Operating code for the microprocessor may be stored in the memory array, possibly along with other data (e.g., tracking or statistical data) used or generated by the on-die microprocessor. A wear leveling algorithm may result in some number of rows within the memory array not being used to store user data at any given time, and these rows may be used to store the operating code and possibly other data for the on-die microprocessor. The on-die microprocessor may boot and run based on the operating code stored in memory array.

公开(公告)号：US20230410873A1

公开(公告)日：2023-12-21

申请号：US18456152

申请日：2023-08-25

Applicant: Micron Technology, Inc.

Inventor： David Hulton ,  Jeremy Chritz ,  Jonathan D. Harms

IPC: G11C11/406 ,  G06F11/07 ,  G06F16/2458 ,  G11C11/4096

CPC classification number: G11C11/406 ,  G06F11/073 ,  G06F11/076 ,  G06F16/2465 ,  G11C11/4096 ,  G06F11/0787 ,  G06F2216/03 ,  G06Q20/0655

Abstract: Methods and apparatus for utilizing non-traditional (e.g., probabilistic or statistically-based) refresh schemes in non-volatile memory. In one embodiment, the memory is characterized in terms of its performance, such as based on BER (bit error rate) as a function of refresh rate based on statistical data for decay of capacitance within the cells of the device with time. In one variant, error-tolerant applications make use of the non-traditionally refreshed (or unrefreshed) memory with enhanced memory bandwidth, since refresh operations have been reduced or eliminated. In another variant, an extant refresh scheme is modified based on a specified minimum allowable performance level for the memory device, In yet another embodiment, error-intolerant applications operate the memory with a reduced or eliminated refresh, and cells or regions of the memory not adequately refreshed by presumed random read/write operations of the memory over time are actively refreshed.

公开(公告)号：US20220351770A1

公开(公告)日：2022-11-03

申请号：US17867124

申请日：2022-07-18

Applicant: Micron Technology, Inc.

Inventor： Jonathan D. Harms ,  David Hulton ,  Jeremy Chritz

IPC: G11C11/406 ,  G06F11/10 ,  G11C29/02 ,  G11C29/52

Abstract: Methods and apparatus for dynamically adjusting performance of partitioned memory. In one embodiment, the method includes receiving one or more configuration requests for the memory device, determining whether to grant the one or more configuration requests for the memory device, in response to the determining, implementing the one or more configuration requests within the memory device and operating the memory device in accordance with the implementing. The adjusting of the performance for the partitioned memory includes one or more of enabling/disabling refresh operations, altering a refresh rate for the partitioned memory, enabling/disabling error correcting code (ECC) circuitry for the partitioned memory, and/or altering a memory cell architecture for the partitioned memory. Systems and applications that may benefit from the dynamic adjustment of performance are also disclosed.

公开(公告)号：US20220108927A1

公开(公告)日：2022-04-07

申请号：US17644414

申请日：2021-12-15

Applicant: Micron Technology, Inc.

Inventor： Nikolay A. Mirin ,  Robert Dembi ,  Richard T. Housley ,  Xiaosong Zhang ,  Jonathan D. Harms ,  Stephen J. Kramer

IPC: H01L21/66 ,  H01L23/544 ,  H01L21/302 ,  H01L21/68

Abstract: A method for measuring overlay between an interest level and a reference level of a wafer includes applying a magnetic field to a wafer, detecting at least one residual magnetic field emitted from at least one registration marker of a first set of registration markers within the wafer, responsive to the detected one or more residual magnetic fields, determining a location of the at least one registration marker of the first set registration markers, determining a location of at least one registration marker of a second set of registration markers, and responsive to the respective determined locations of the at least one registration marker of the first set of registration markers and the at least one registration marker of the second set of registration markers, calculating a positional offset between an interest level of the wafer and a reference level of the wafer. Related methods and systems are also disclosed.

公开(公告)号：US20220076726A1

公开(公告)日：2022-03-10

申请号：US17013402

申请日：2020-09-04

Applicant: Micron Technology, Inc.

Inventor： David N. Hulton ,  Jeremy Chritz ,  Jonathan D. Harms

IPC: G11C11/406 ,  G06F11/07 ,  G06F16/2458 ,  G11C11/4096

Abstract: Methods and apparatus for utilizing non-traditional (e.g., probabilistic or statistically-based) refresh schemes in non-volatile memory. In one embodiment, the memory is characterized in terms of its performance, such as based on BER (bit error rate) as a function of refresh rate based on statistical data for decay of capacitance within the cells of the device with time. In one variant, error-tolerant applications make use of the non-traditionally refreshed (or unrefreshed) memory with enhanced memory bandwidth, since refresh operations have been reduced or eliminated. In another variant, an extant refresh scheme is modified based on a specified minimum allowable performance level for the memory device, In yet another embodiment, error-intolerant applications operate the memory with a reduced or eliminated refresh, and cells or regions of the memory not adequately refreshed by presumed random read/write operations of the memory over time are actively refreshed.

公开(公告)号：US20220067544A1

公开(公告)日：2022-03-03

申请号：US17005036

申请日：2020-08-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yi Hu ,  Dmitry Vengertsev ,  Zahra Hosseinimakarem ,  Jonathan D. Harms

IPC: G06N5/04 ,  G06T7/90 ,  G06T7/00 ,  G06T7/521 ,  G06N20/00 ,  G06T11/00

Abstract: An image or a spectrum of a surface may be acquired by a computing device, which may be included in a mobile device in some examples. The computing device may extract a measured spectrum from the image and generate a corrected spectrum of the surface. In some examples, the corrected spectrum may be generated to compensate for ambient light influence. The corrected spectrum may be analyzed to provide a result, such as a diagnosis or a product recommendation. In some examples, the result is based, at least in part, on a comparison of the corrected spectrum to reference spectra. In some examples, the result is based, at least in part, on an inference of a machine learning model.

公开(公告)号：US20210407615A1

公开(公告)日：2021-12-30

申请号：US16914927

申请日：2020-06-29

Applicant: Micron Technology, Inc.

Inventor： Troy A. Manning ,  Troy D. Larsen ,  Jonathan D. Harms ,  Glen E. Hush ,  Timothy P. Finkbeiner

IPC: G11C29/44 ,  G11C29/42 ,  G11C29/00 ,  G11C29/18

Abstract: Methods, systems, and devices for modifiable repair solutions for a memory array are described to support storing repair information for a memory array within the memory array itself. A memory device may include the memory array and an on-die microprocessor, where the microprocessor may retrieve the repair information from the memory array and write the repair information to repair circuitry used for identifying defective memory addresses. The microprocessor may support techniques for identifying additional defects and updating the repair information during operation of the memory array. For example, the microprocessor may identify additional defects based on errors associated with one or more memory cells of the memory array or based on testing performed on one or more memory cells of the memory array. In some cases, a host device may identify additional defects and may notify the microprocessor of the additional defects.