公开(公告)号：US20190129856A1

公开(公告)日：2019-05-02

申请号：US15797812

申请日：2017-10-30

Applicant: Micron Technology, Inc.

Inventor： Sebastien Andre Jean

IPC: G06F12/0871 ,  G06F12/02 ,  G06F9/50 ,  G06F9/54

CPC classification number: G06F12/0871 ,  G06F9/5016 ,  G06F9/544 ,  G06F12/0246 ,  G06F2212/1021 ,  G06F2212/222 ,  G06F2212/502 ,  G06F2212/7201

Abstract: Disclosed in some examples are methods, systems, and machine readable mediums that dynamically adjust the size of an L2P cache in a memory device in response to observed operational conditions. The L2P cache may borrow memory space from a donor memory location, such as a read or write buffer. For example, if the system notices a high amount of read requests, the system may increase the size of the L2P cache at the expense of the write buffer (which may be decreased). Likewise, if the system notices a high amount of write requests, the system may increase the size of the L2P cache at the expense of the read buffer (which may be decreased).

公开(公告)号：US20190108878A1

公开(公告)日：2019-04-11

申请号：US16209152

申请日：2018-12-04

Applicant: Micron Technology, Inc.

Inventor： Sebastien Andre Jean ,  Ting Luo

IPC: G11C11/56 ,  G11C16/34

Abstract: Devices and techniques to reduce corruption of received data during assembly are disclosed herein. A memory device can perform operations to store received data, including preloaded data, in a first mode until the received data exceeds a threshold amount, and to transition from the first mode to a second mode after the received data exceeds the threshold amount.

公开(公告)号：US11756638B2

公开(公告)日：2023-09-12

申请号：US17232804

申请日：2021-04-16

Applicant: Micron Technology, Inc.

Inventor： Sebastien Andre Jean

IPC: G11C16/34 ,  G01R31/3193 ,  G11C29/52 ,  G11C29/44 ,  G11C29/56

CPC classification number: G11C16/3495 ,  G01R31/31935 ,  G11C29/52 ,  G11C2029/4402 ,  G11C2029/5606

Abstract: Disclosed in some examples are methods, systems, memory devices, machine readable mediums configured to intentionally degrade NAND performance when a value of a NAND health metric indicates a potential for failure to encourage users to replace or backup their devices before data loss occurs. For example, the system may track a NAND health metric and when that metric reaches a predetermined threshold or state, the system may intentionally degrade performance. This performance degradation may be more effective than a warning to effect device backup or replacement.

公开(公告)号：US11727997B2

公开(公告)日：2023-08-15

申请号：US16628453

申请日：2018-06-29

Applicant: Micron Technology, Inc.

Inventor： Greg A. Blodgett ,  Sebastien Andre Jean

IPC: G06F12/14 ,  G06F3/06 ,  G06F12/02 ,  G06F21/79 ,  G11C16/34 ,  G11C16/04 ,  G06F1/3206 ,  G11C7/04 ,  G06F9/30 ,  G06F9/32 ,  G06F9/54 ,  H04L9/08 ,  G06F1/3234 ,  G11C16/10

CPC classification number: G11C16/3418 ,  G06F1/3206 ,  G06F1/3275 ,  G06F3/0622 ,  G06F3/0659 ,  G06F3/0679 ,  G06F9/30101 ,  G06F9/321 ,  G06F9/546 ,  G06F12/0246 ,  G06F12/1408 ,  G06F12/1416 ,  G06F12/1425 ,  G06F12/1441 ,  G06F12/1458 ,  G06F12/1466 ,  G06F21/79 ,  G11C7/04 ,  G11C16/0408 ,  G11C16/0483 ,  G11C16/3427 ,  H04L9/0861 ,  G11C16/10 ,  G11C16/3459 ,  G11C2213/71

Abstract: Apparatus and methods are disclosed, including a memory device or a memory controller configured to supply supported voltages to a host, provide temperature throttling information to the host, or provide an indication that a host attempting to read a result was not the host that caused the placement of the result in a result register. Methods of operation are disclosed, as well as machine-readable medium and other embodiments.

公开(公告)号：US20220358034A1

公开(公告)日：2022-11-10

申请号：US17869313

申请日：2022-07-20

Applicant: Micron Technology, Inc.

Inventor： Sebastien Andre Jean ,  Greg A. Blodgett

IPC: G06F12/02 ,  G06F3/06 ,  G06F12/14

Abstract: Devices and techniques for host accelerated operations in managed NAND devices are described herein. A host logical-to-physical (L2P) table of the NAND device has an associated map. Entries in the map correspond to one or more logical addresses (LA) and indicate whether the host L2P table is current for those LAs. If the table is not current, then a request will bypass the host L2P table, using a standard device L2P lookup instead. Otherwise, the host L2P table can be used.

公开(公告)号：US11237737B2

公开(公告)日：2022-02-01

申请号：US16773334

申请日：2020-01-27

Applicant: Micron Technology, Inc.

Inventor： Kulachet Tanpairoj ,  Sebastien Andre Jean ,  Kishore Kumar Muchherla ,  Ashutosh Malshe ,  Jianmin Huang

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/0811 ,  G06F12/02

Abstract: Disclosed in some examples are memory devices which feature customizable Single Level Cell (SLC) and Multiple Level Cell (MLC) configurations. The SLC memory cells serve as a high-speed cache providing SLC level performance with the storage capacity of a memory device with MLC memory cells. The proportion of cells configured as MLC vs the proportion that are configured as SLC storage may be configurable, and in some examples, the proportion may change during usage based upon configurable rules based upon memory device metrics. In some examples, when the device activity is below an activity threshold, the memory device may skip the SLC cache and place the data directly into the MLC storage to reduce power consumption.

公开(公告)号：US20210279009A1

公开(公告)日：2021-09-09

申请号：US17331228

申请日：2021-05-26

Applicant: Micron Technology, Inc.

Inventor： Sebastien Andre Jean

IPC: G06F3/06 ,  G11C16/04 ,  G11C16/10

Abstract: Apparatus and methods are disclosed, including maintaining a first group of tagged data from a host device at contiguous physical locations on a group of non-volatile memory cells of a storage system during system management operations on the group of non-volatile memory cells including the first group of tagged data while the first group of tagged data remains stored on the storage system and prioritizing, in the storage system, commands associated with the first group of tagged data.

公开(公告)号：US11074009B2

公开(公告)日：2021-07-27

申请号：US16012728

申请日：2018-06-19

Applicant: Micron Technology, Inc.

Inventor： Sebastien Andre Jean

IPC: G06F3/06 ,  G11C16/10 ,  G11C16/04

Abstract: Apparatus and methods are disclosed, including identifying inactive data in a group of volatile memory cells of a host device, assembling identified inactive data in an offload unit of the group of volatile memory cells, and writing the offload unit of inactive data to a group of non-volatile memory cells of a storage system when the amount of inactive data in the offload unit reaches a threshold.

公开(公告)号：US20210181994A1

公开(公告)日：2021-06-17

申请号：US17188692

申请日：2021-03-01

Applicant: Micron Technology, Inc.

Inventor： Sebastien Andre Jean

IPC: G06F3/06 ,  G06F12/10 ,  G06F12/14

Abstract: Devices and techniques for host accelerated operations in managed NAND devices are described herein. A read request is received at a controller of a NAND device. Here, the read request includes a logical address and a physical address. A a verification component that corresponds to the physical address is retrieved a NAND array of the NAND device. A verification of the read request is computed using the logical address, the physical address, and the verification component. A read operation is then modified based on the verification.

公开(公告)号：US20210134376A1

公开(公告)日：2021-05-06

申请号：US17147222

申请日：2021-01-12

Applicant: Micron Technology, Inc.

Inventor： Greg A. Blodgett ,  Sebastien Andre Jean

IPC: G11C16/34 ,  G11C16/04 ,  G06F1/3206 ,  G11C7/04 ,  G06F12/14 ,  G06F3/06 ,  G06F9/30 ,  G06F9/32 ,  G06F9/54 ,  G06F12/02 ,  G06F21/79 ,  H04L9/08

Abstract: Apparatus and methods are disclosed, including a memory device or a memory controller configured to determine that a condition has occurred that indicates a performance throttling operation, implement a performance throttling responsive to the determined condition, responsive to implementing the performance throttling, set a performance throttling status indicator in an exception event status attribute, receive a command from a host device across a memory device interface, perform the command, prepare a response to the command, the response including a flag indicating that the performance throttling status indicator is set in the exception event status attribute, and send the response to the host device. Methods of operation are disclosed, as well as machine-readable medium and other embodiments.