公开(公告)号：US09748184B2

公开(公告)日：2017-08-29

申请号：US14883632

申请日：2015-10-15

Applicant: Micron Technology, Inc.

Inventor： Shing-Yih Shih ,  Hsu Chiang

IPC: H01L23/00 ,  H01L23/58 ,  H01L23/552 ,  H01L25/065 ,  H01L23/498

CPC classification number: H01L23/585 ,  H01L21/6835 ,  H01L21/6836 ,  H01L22/14 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/552 ,  H01L23/562 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68331 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81192 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2924/37001 ,  H01L2224/81 ,  H01L2224/83

Abstract: A semiconductor device includes an interposer having a first side and a second side opposite to the first side; a first semiconductor die mounted on the first side within a first chip mounting area through a plurality of first bumps; a second semiconductor die mounted on the first side within a second chip mounting area being adjacent to the first chip mounting area; a ring-shaped supporting feature disposed on the first side and encompassing the first chip mounting area and the second chip mounting area; and a plurality of solder bumps mounted on the second side.

公开(公告)号：US20170213801A1

公开(公告)日：2017-07-27

申请号：US15003812

申请日：2016-01-22

Applicant: Micron Technology, Inc.

Inventor： Tieh-Chiang Wu ,  Shing-Yih Shih

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L21/78

CPC classification number: H01L24/02 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/147 ,  H01L23/15 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3171 ,  H01L23/49811 ,  H01L23/49827 ,  H01L25/105 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2224/0231 ,  H01L2224/02331 ,  H01L2224/02333 ,  H01L2224/0235 ,  H01L2224/02373 ,  H01L2224/024 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/48225 ,  H01L2224/81005 ,  H01L2224/81193 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2224/81

Abstract: A method for fabricating a package-on-package assembly is provided. A carrier with a passivation layer on the carrier is provided. A redistribution layer (RDL) is formed on the passivation layer. The RDL comprises at least one dielectric layer and at least one metal layer. The at least one metal layer comprises a plurality of first bump pads and second bump pads exposed from a top surface of the at least one dielectric layer. The first bump pads are disposed within a chip mounting area, while the second pads are disposed within a peripheral area. At least one chip is then mounted on the first bump pads. The at least one chip is electrically connected to the RDL through first bumps on the first bump pads. A die package is then mounted on the second bump pads. The die package is electrically connected to the RDL through second bumps on the second bump pads.