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    Array Of Cross Point Memory Cells And Methods Of Forming An Array Of Cross Point Memory Cells
    51.
    发明申请
    Array Of Cross Point Memory Cells And Methods Of Forming An Array Of Cross Point Memory Cells 审中-公开

    公开(公告)号：US20180138239A1

    公开(公告)日：2018-05-17

    申请号：US15851112

    申请日：2017-12-21

    Applicant: Micron Technology, Inc.

    Inventor： Fabio Pellizzer ,  Stephen W. Russell ,  Tony M. Lindenberg

    IPC: H01L27/24 ,  H01L45/00

    Abstract: An array of cross point memory cells comprises spaced elevationally inner first lines, spaced elevationally outer second lines which cross the first lines, and a multi-resistive state region elevationally between the first and second lines where such cross. Individual of the multi-resistive state regions comprise elevationally outer multi-resistive state material and elevationally inner multi-resistive state material that are electrically coupled to one another. The inner multi-resistive state material has opposing edges in a vertical cross-section. The outer multi-resistive state material has opposing edges in the vertical cross-section that are laterally offset relative to the opposing edges of the inner multi-resistive state material in the vertical cross-section. Methods are also disclosed.

    Memory Cells and Methods of Forming Memory Cells
    55.
    发明申请
    Memory Cells and Methods of Forming Memory Cells 有权
    记忆细胞和形成记忆细胞的方法

    公开(公告)号：US20150041749A1

    公开(公告)日：2015-02-12

    申请号：US13959958

    申请日：2013-08-06

    Applicant: Micron Technology, Inc.

    Inventor： Lequn Jennifer Liu ,  Stephen W. Russell ,  Fabio Pellizzer ,  Swapnil Lengade

    IPC: H01L45/00

    CPC classification number: H01L45/165 ,  H01L27/2427 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/144 ,  H01L45/1675

    Abstract: A method of forming a memory cell includes forming an outer electrode material elevationally over and directly against a programmable material. The programmable material and the outer electrode material contact one another along an interface. Protective material is formed elevationally over the outer electrode material. Dopant is implanted through the protective material into the outer electrode material and the programmable material and across the interface to enhance adhesion of the outer electrode material and the programmable material relative one another across the interface. Memory cells are also disclosed.

    Abstract translation: 一种形成存储单元的方法包括在外部电极材料上形成并且直接抵靠可编程材料。 可编程材料和外部电极材料沿着界面彼此接触。 保护材料在外部电极材料上垂直地形成。 通过保护材料将掺杂剂注入到外部电极材料和可编程材料中并跨越界面，以增强外部电极材料和可编程材料相对于界面的粘合性。 还公开了存储单元。

    Methods of Forming Memory Cells; and Methods of Forming Vertical Structures
    56.
    发明申请
    Methods of Forming Memory Cells; and Methods of Forming Vertical Structures 有权
    形成记忆细胞的方法 和垂直结构形成方法

    公开(公告)号：US20140087558A1

    公开(公告)日：2014-03-27

    申请号：US14097003

    申请日：2013-12-04

    Applicant: Micron Technology, Inc.

    Inventor： David A. Kewley ,  Brian Cleereman ,  Stephen W. Russell ,  Rex Stone ,  Anthony C. Krauth

    IPC: H01L21/3213 ,  H01L21/28

    CPC classification number: H01L21/32133 ,  H01L21/0337 ,  H01L21/28008 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/32139 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568

    Abstract: Some embodiments include methods of forming memory. A series of photoresist features may be formed over a gate stack, and a placeholder may be formed at an end of said series. The placeholder may be spaced from the end of said series by a gap. A layer may be formed over and between the photoresist features, over the placeholder, and within said gap. The layer may be anisotropically etched into a plurality of first vertical structures along edges of the photoresist features, and into a second vertical structure along an edge of the placeholder. A mask may be formed over the second vertical structure. Subsequently, the first vertical structures may be used to pattern string gates while the mask is used to pattern a select gate. Some embodiments include methods of forming conductive runners, and some embodiments may include semiconductor constructions.

    Abstract translation: 一些实施例包括形成存储器的方法。 可以在栅极堆叠上形成一系列光致抗蚀剂特征，并且可以在所述串联的末端形成占位符。 占位符可以通过间隙与所述系列的端部间隔开。 可以在光致抗蚀剂特征之上和之间在占位符上方以及在所述间隙内形成层。 该层可以沿光致抗蚀剂特征的边缘各向异性地蚀刻成多个第一垂直结构，并且沿着占位符的边缘进入第二垂直结构。 可以在第二垂直结构上形成掩模。 随后，可以使用第一垂直结构来模拟串门，同时使用掩模来对选择门进行图案化。 一些实施例包括形成导电流道的方法，并且一些实施例可以包括半导体结构。

    METHODS TO INCREASE CELL DENSITY USING A LATERAL ETCH
    57.
    发明公开
    METHODS TO INCREASE CELL DENSITY USING A LATERAL ETCH 审中-公开

    公开(公告)号：US20240357815A1

    公开(公告)日：2024-10-24

    申请号：US18637127

    申请日：2024-04-16

    Applicant: Micron Technology, Inc.

    Inventor： Paolo Fantini ,  Lorenzo Fratin ,  Paolo Tessariol ,  Enrico Varesi ,  Emilio Camerlenghi ,  Stephen W. Russell ,  Yoshiaki Fukuzumi

    IPC: H10B43/27

    CPC classification number: H10B43/27

    Abstract: Methods, systems, and devices for methods to increase cell density using a lateral etch are described. A process to manufacture a memory array may include a lateral wet etch to split a pillar into two stacks of memory cells. In some cases, the manufacturing process may include forming a trench in a vertical stack of layers and forming a memory cell pillar which includes an oxide material, a semiconductor channel material, and an insulating material in the trench. Sidewalls of the pillar may be laterally etched to remove portions of the oxide material and the semiconductor material, which may form two stacks of memory cells, each stack in contact with opposing sidewalls of the trench. In some examples, the manufacturing process may include forming one or more supportive piers within the trench, and the pillar of memory cell material may be formed between pairs of piers.

    CROSS-POINT MEMORY ARRAY WITH ACCESS LINES
    59.
    发明公开
    CROSS-POINT MEMORY ARRAY WITH ACCESS LINES 审中-公开

    公开(公告)号：US20240292632A1

    公开(公告)日：2024-08-29

    申请号：US18657259

    申请日：2024-05-07

    Applicant: Micron Technology, Inc.

    Inventor： Hernan A. Castro ,  Stephen H. Tang ,  Stephen W. Russell

    IPC: H10B63/00 ,  H10B53/20 ,  H10N70/20

    CPC classification number: H10B63/845 ,  H10B53/20 ,  H10B63/20 ,  H10B63/22 ,  H10B63/24 ,  H10B63/80 ,  H10B63/84 ,  H10N70/235 ,  H10N70/245

    Abstract: Methods and apparatuses for a cross-point memory array and related fabrication techniques are described. The fabrication techniques described herein may facilitate concurrently building two or more decks of memory cells disposed in a cross-point architecture. Each deck of memory cells may include a plurality of first access lines (e.g., word lines), a plurality of second access lines (e.g., bit lines), and a memory component at each topological intersection of a first access line and a second access line. The fabrication technique may use a pattern of vias formed at a top layer of a composite stack, which may facilitate building a 3D memory array within the composite stack while using a reduced number of processing steps. The fabrication techniques may also be suitable for forming a socket region where the 3D memory array may be coupled with other components of a memory device.

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