公开(公告)号：US11081158B2

公开(公告)日：2021-08-03

申请号：US16813334

申请日：2020-03-09

Applicant: Micron Technology, Inc.

Inventor： Hyun Yoo Lee ,  Suryanarayana B. Tatapudi ,  Huy T. Vo ,  Ferdinando Bedeschi ,  Umberto Di Vincenzo ,  Riccardo Muzzetto

IPC: G11C11/22 ,  G11C11/4094 ,  G11C11/4091

Abstract: Methods, systems, and devices for a source follower-based sensing architecture and sensing scheme are described. In one example, a memory device may include a sense circuit that includes two source followers that are coupled to each other and to a sense amplifier. A method of operating the memory device may include transferring a digit line voltage to one of the source followers and transferring a reference voltage to the other source follower. After transferring the digit line voltage and the reference voltage, the source followers may be enabled so that signals representative of the digit line voltage and the reference voltage are transferred from the outputs of the source followers to the sense amplifier for sensing.

公开(公告)号：US11017831B2

公开(公告)日：2021-05-25

申请号：US16511423

申请日：2019-07-15

Applicant: Micron Technology, Inc.

Inventor： Umberto Di Vincenzo

IPC: G11C11/22

Abstract: Methods, systems, and devices for accessing a ferroelectric memory cell are described. In some examples, during a first portion of an access procedure, the voltages of a digit line and word line coupled with the memory cell may be increased while the voltage of a plate coupled with the memory cell is held constant, which may support sensing a logic state stored by the memory cell prior the access procedure, and which may result in a first logic state being written to the memory cell. A voltage of the plate may then be increased, and the digit line may then be coupled with the plate. Because the first logic state was previously written to the memory cell, a target logic state may not need to be subsequently written to the memory cell unless different than the first logic state.

公开(公告)号：US10978126B2

公开(公告)日：2021-04-13

申请号：US16184480

申请日：2018-11-08

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati ,  Scott James Derner ,  Umberto Di Vincenzo ,  Christopher Johnson Kawamura ,  Eric S. Carman

IPC: G11C11/22

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A ground reference scheme may be employed in a digit line voltage sensing operation. A positive voltage may be applied to a memory cell; and after a voltage of the digit line of the cell has reached a threshold, a negative voltage may be applied to cause the digit line voltages to center around ground before a read operation. In another example, a first voltage may be applied to a memory cell and then a second voltage that is equal to an inverse of the first voltage may be applied to a reference capacitor that is in electronic communication with a digit line of the memory cell to cause the digit line voltages to center around ground before a read operation.

公开(公告)号：US10950308B2

公开(公告)日：2021-03-16

申请号：US16927473

申请日：2020-07-13

Applicant: Micron Technology, Inc.

Inventor： Marco Sforzin ,  Umberto Di Vincenzo

IPC: G11C11/34 ,  G11C16/12 ,  G11C16/28 ,  G11C7/14 ,  G11C11/24 ,  G11C7/06 ,  G11C11/404 ,  G11C13/00 ,  G11C11/56

Abstract: A counter can have a number of sensing components. Each respective sensing component can be configured to sense a respective event and can include a respective first capacitor configured to be selectively coupled to a second capacitor in response to the respective sensing component sensing the respective event. The second capacitor can be configured to be charged to a voltage by each respective first capacitor that is selectively coupled to the second capacitor. The counter can have a comparator with a first input coupled to the second capacitor and a second input coupled to a reference voltage corresponding to a threshold quantity of events. The comparator can be configured to output a signal indicative of the threshold quantity of events being sensed in response to the voltage of the second capacitor being greater than or equal to the reference voltage.

公开(公告)号：US10607676B2

公开(公告)日：2020-03-31

申请号：US15962941

申请日：2018-04-25

Applicant: Micron Technology, Inc.

Inventor： Umberto Di Vincenzo

IPC: G11C11/22 ,  G11C11/24

Abstract: Devices and methods for sensing a memory cell are described. The memory cell may include a ferroelectric memory cell. During a read operation, a cascode may couple a precharged capacitor with the memory cell to transfer a charge between the precharged capacitor and the memory cell. The cascode may isolate the capacitor from the memory cell based on the charge transferred between the capacitor and the memory cell. A second capacitor (e.g., a parasitic capacitor) may continue to provide an additional amount of charge to the memory cell during the read operation. Such a change in capacitance value during the read operation may provide a large sense window due to a non-linear voltage characteristics associated with the change in capacitance value.

公开(公告)号：US10446214B1

公开(公告)日：2019-10-15

申请号：US16102053

申请日：2018-08-13

Applicant: Micron Technology, Inc.

Inventor： Umberto Di Vincenzo ,  Ferdinando Bedeschi ,  Riccardo Muzzetto

IPC: G11C11/22

Abstract: Methods and devices for reading a memory cell using a sense amplifier with split capacitors is described. The sense amplifier may include a first capacitor and a second capacitor that may be configured to provide a larger capacitance during certain portions of a read operation and a lower capacitance during other portions of the read operation. In some cases, the first capacitor and the second capacitor are configured to be coupled in parallel between a signal node and a voltage source during a first portion of the read operation to provide a higher capacitance. The first capacitor may be decoupled from the second capacitor during a second portion of the read operation to provide a lower capacitance during the second portion.

公开(公告)号：US10403336B2

公开(公告)日：2019-09-03

申请号：US15857091

申请日：2017-12-28

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Umberto Di Vincenzo

IPC: G11C7/12 ,  G11C11/22

Abstract: Methods and devices for techniques for precharging a memory cell are described. Precharging a memory cell while the memory cell is coupled with its digit line may reduce a total duration of an access operation thereby reducing a latency associated with accessing a memory device. During a read operation, the memory device may select a word line to couple the memory cell with a selected digit line. Further, the memory device may selectively couple the selected digit line with a reference digit line that is to be precharged to a given voltage. A difference in voltage between the selected digit line and the reference digit line at the completion of precharging may represent a signal indicative of a logic state of the memory cell. The memory device may use a capacitor precharged to a first voltage to capture the signal. In some cases, the memory device may continue to perform a self-reference operation using the same memory cell, the selected digit line, and the reference digit line to produce a reference signal using the capacitor precharged to a different voltage. A similar precharging steps may be repeated during the self-reference operation. The selected word line may remain activated during the read operation and the self-reference operation.

公开(公告)号：US20190206455A1

公开(公告)日：2019-07-04

申请号：US15857091

申请日：2017-12-28

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Umberto Di Vincenzo

IPC: G11C7/12 ,  G11C11/22

CPC classification number: G11C7/12 ,  G11C11/221 ,  G11C11/2255 ,  G11C11/2273 ,  G11C11/2293

Abstract: Methods and devices for techniques for precharging a memory cell are described. Precharging a memory cell while the memory cell is coupled with its digit line may reduce a total duration of an access operation thereby reducing a latency associated with accessing a memory device. During a read operation, the memory device may select a word line to couple the memory cell with a selected digit line. Further, the memory device may selectively couple the selected digit line with a reference digit line that is to be precharged to a given voltage. A difference in voltage between the selected digit line and the reference digit line at the completion of precharging may represent a signal indicative of a logic state of the memory cell. The memory device may use a capacitor precharged to a first voltage to capture the signal. In some cases, the memory device may continue to perform a self-reference operation using the same memory cell, the selected digit line, and the reference digit line to produce a reference signal using the capacitor precharged to a different voltage. A similar precharging steps may be repeated during the self-reference operation. The selected word line may remain activated during the read operation and the self-reference operation.

公开(公告)号：US20190189211A1

公开(公告)日：2019-06-20

申请号：US15846373

申请日：2017-12-19

Applicant: Micron Technology, Inc.

Inventor： Umberto Di Vincenzo ,  Riccardo Muzzetto ,  Ferdinando Bedeschi

IPC: G11C14/00 ,  G11C11/22

CPC classification number: G11C14/0027 ,  G11C11/221 ,  G11C11/2273 ,  G11C11/2293

Abstract: The present disclosure includes apparatuses, methods, and systems for charge separation for memory sensing. An embodiment includes applying a sensing voltage to a memory cell, and determining a data state of the memory cell based, at least in part, on a comparison of an amount of charge discharged by the memory cell while the sensing voltage is being applied to the memory cell before a particular reference time and an amount of charge discharged by the memory cell while the sensing voltage is being applied to the memory cell after the particular reference time.

公开(公告)号：US20190067206A1

公开(公告)日：2019-02-28

申请号：US15691055

申请日：2017-08-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Ferdinando Bedeschi ,  Umberto Di Vincenzo ,  Daniele Vimercati

IPC: H01L23/552 ,  H01L23/528 ,  H01L27/108 ,  H01L27/11507 ,  G11C11/22 ,  G11C11/4091 ,  G11C11/409

CPC classification number: H01L23/552 ,  G11C7/08 ,  G11C7/1051 ,  G11C7/1096 ,  G11C11/1653 ,  G11C11/1659 ,  G11C11/221 ,  G11C11/2253 ,  G11C11/2255 ,  G11C11/2257 ,  G11C11/2259 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/408 ,  G11C11/4085 ,  G11C11/409 ,  G11C11/4091 ,  G11C11/4094 ,  G11C13/0023 ,  G11C13/003 ,  G11C2213/82 ,  H01L23/528 ,  H01L27/10805 ,  H01L27/10885 ,  H01L27/11507 ,  H01L27/11514

Abstract: Apparatuses and methods for memory that includes a first memory cell including a storage component having a first end coupled to a plate line and a second end coupled to a digit line, and a second memory cell including a storage component having a first end coupled to a digit line and a second end coupled to a plate line, wherein the digit line of the second memory cell is adjacent to the plate line of the first memory cell.