公开(公告)号：US20200098421A1

公开(公告)日：2020-03-26

申请号：US16138115

申请日：2018-09-21

申请人： Micron Technology, Inc.

发明人： Gianni Stephen Alsasua ,  Harish Reddy Singidi ,  Kishore Kumar Muchherla ,  Sampath Ratnam ,  Ashutosh Malshe ,  Vamsi Pavan Rayaprolu ,  Renato Padilla, JR.

IPC分类号： G11C11/406 ,  G06F13/16

摘要： Devices and techniques for temperature informed memory refresh are described herein. Temperature data can be updated in response to a memory component write performed under an extreme temperature. Here, the write is performed on a memory component element in the memory component. The memory component element can be sorted above other memory component elements in the memory component based on the temperature data. Once sorted to the top of these memory component elements, a refresh can be performed the memory component element.

公开(公告)号：US20200097211A1

公开(公告)日：2020-03-26

申请号：US16138334

申请日：2018-09-21

申请人： Micron Technology, Inc.

发明人： Gianni Stephen Alsasua ,  Harish Reddy Singidi ,  Peter Sean Feeley ,  Ashutosh Malshe ,  Renato Padilla, JR. ,  Kishore Kumar Muchherla ,  Sampath Ratnam

IPC分类号： G06F3/06 ,  G11C16/34

摘要： Systems and methods are disclosed, comprising a memory device comprising multiple groups of memory cells, the groups comprising a first group of memory cells and a second group of memory cells configured to store information at a same bit capacity per memory cell, and a processing device operably coupled to the memory device, the processing device configured to adjust a scan event threshold for one of the first or second groups of memory cells to a threshold less than a target scan event threshold for the first and second groups of memory cells to distribute scan events in time on the memory device.

公开(公告)号：US20200058327A1

公开(公告)日：2020-02-20

申请号：US16518651

申请日：2019-07-22

申请人： Micron Technology, Inc.

发明人： Tyson M. Stichka ,  Preston Allen Thomson ,  Scott Anthony Stoller ,  Christopher Bueb ,  Jianmin Huang ,  Kulachet Tanpairoj ,  Harish Reddy Singidi

IPC分类号： G11C5/00 ,  G11C7/04 ,  G11C16/04 ,  G11C16/26 ,  G11C16/10 ,  G11C11/56 ,  G11C16/34 ,  G11C7/10

摘要： Devices and techniques for NAND cell encoding to improve data integrity are disclosed herein. A high-temperature indicator is obtained and a write operation is received. The write operation is then performed on a NAND cell using a modified encoding in response to the high-temperature indicator. The modified encoding includes a reduced number of voltage distribution positions from an unmodified encoding without changing voltage distribution widths, where each voltage distribution corresponds to a discrete set of states an encoding.

公开(公告)号：US20200042201A1

公开(公告)日：2020-02-06

申请号：US16506372

申请日：2019-07-09

申请人： Micron Technology, Inc.

发明人： Jianmin Huang ,  Kulachet Tanpairoj ,  Harish Reddy Singidi ,  Ting Luo

IPC分类号： G06F3/06 ,  G06F12/02 ,  G06F12/1009 ,  G06F12/1027

摘要： Devices and techniques for managing partial superblocks in a NAND device are described herein. A set of superblock candidates is calculated. Here, a superblock may have a set of blocks that share a same position in each plane in each die of a NAND array of the NAND device. A set of partial super block candidates is also calculated. A partial superblock candidate is a superblock candidate that has at least one plane that has a bad block. A partial superblock use classification may then be obtained. Superblocks may be established for the NAND device by using members of the set of superblock candidates after removing the set of partial superblock candidates from the set of superblock candidates. Partial superblocks may then be established for classes of data in the NAND device according to the partial superblock use classification.

公开(公告)号：US20200005884A1

公开(公告)日：2020-01-02

申请号：US16410764

申请日：2019-05-13

申请人： Micron Technology, Inc.

发明人： Ting Luo ,  Scott Anthony Stoller ,  Preston Allen Thomson ,  Devin Batutis ,  Harish Reddy Singidi ,  Kulachet Tanpairoj

IPC分类号： G11C29/38 ,  G11C29/44 ,  G06F11/07

摘要： Disclosed in some examples are methods, systems, memory devices, and machine readable mediums for performing an erase page check. For example, in response to an unexpected (e.g., an asynchronous) shutdown, the memory device may have one or more cells that did not finish programming. The memory device may detect these cells and erase them or mark them for erasure.

公开(公告)号：US20190295660A1

公开(公告)日：2019-09-26

申请号：US16436567

申请日：2019-06-10

申请人： Micron Technology, Inc.

发明人： Ashutosh Malshe ,  Kishore Kumar Muchherla ,  Harish Reddy Singidi ,  Peter Sean Feeley ,  Sampath Ratnam ,  Kulachet Tanpairoj ,  Ting Luo

IPC分类号： G11C16/26 ,  G11C16/34 ,  G11C29/02 ,  G11C16/04 ,  G11C16/28

摘要： Devices and techniques for read voltage calibration of a flash-based storage system based on host IO operations are disclosed. In an example, a memory device includes a NAND memory array having groups of multiple blocks of memory cells, and a memory controller to optimize voltage calibration for reads of the memory array. In an example, the optimization technique includes monitoring read operations occurring to a respective block, identifying a condition to trigger a read level calibration based on the read operations, and performing the read level calibration for the respective block or a memory component that includes the respective block. In a further example, the calibration is performed based on a threshold voltage to read the respective block, which may be considered when the threshold voltage to read the respective block is evaluated within a sampling operation performed by the read level calibration.

公开(公告)号：US20190259463A1

公开(公告)日：2019-08-22

申请号：US16405192

申请日：2019-05-07

申请人： Micron Technology, Inc.

发明人： Sebastien Andre Jean ,  Harish Reddy Singidi

IPC分类号： G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  G06F13/16 ,  G11C16/30 ,  G11C16/26

摘要： Devices and techniques for voltage degradation aware NAND array management are disclosed herein. Voltage to a NAND device is monitored to detect a voltage event. A history of voltage events is modified with the voltage event. A voltage condition is observed from the history of voltage events. An operational parameter of a NAND array in the NAND device is then modified in response to the voltage condition.

公开(公告)号：US20190237146A1

公开(公告)日：2019-08-01

申请号：US16381682

申请日：2019-04-11

申请人： Micron Technology, Inc.

发明人： Ashutosh Malshe ,  Harish Reddy Singidi ,  Kishore Kumar Muchherla ,  Michael G. Miller ,  Sampath Ratman ,  Xu Zhang ,  Jie Zhou

IPC分类号： G11C16/26 ,  G06F11/22 ,  G06F12/02 ,  G11C7/06 ,  G06F11/07 ,  G11C16/34

摘要： Devices and techniques for initiating and controlling preemptive idle time read scans in a flash based storage system are disclosed. In an example, a memory device includes a NAND memory array and a memory controller to schedule and initiate read scans among multiple locations of the memory array, with such read scans being preemptively triggered during an idle (background) state of the memory device, thus reducing host latency during read and write operations in an active (foreground) state of the memory device. In an example, the optimization technique includes scheduling a read scan operation, monitoring an active or idle state of host IO operations, and preemptively initiating the read scan operation when entering an idle state, before the read scan operation is scheduled to occur. In further examples, the read scan may preemptively occur based on time-based scheduling, frequency-based conditions, or event-driven conditions triggering the read scan.

公开(公告)号：US11417405B2

公开(公告)日：2022-08-16

申请号：US17141964

申请日：2021-01-05

申请人： Micron Technology, Inc.

发明人： Ankit Vinod Vashi ,  Harish Reddy Singidi ,  Kishore Kumar Muchherla

IPC分类号： G11C16/34 ,  G11C11/406 ,  G11C16/26 ,  G11C29/10 ,  G06F11/00 ,  G11C16/10

摘要： A variety of applications can include systems and/or methods of optimizing results from scanning a memory device, where the memory device has stacked multiple reliability specifications. Information about a block of multiple blocks of a memory device can be logged, where the information is associated with a combination of reliability specifications. A refresh of the block can be triggered based on exceeding a threshold condition for the combination of reliability specifications.

公开(公告)号：US20220221993A1

公开(公告)日：2022-07-14

申请号：US17708735

申请日：2022-03-30

申请人： Micron Technology, Inc.

发明人： Xiangang Luo ,  Harish Reddy Singidi ,  Ting Luo ,  Kishore Kumar Muchherla

IPC分类号： G06F3/06

摘要： Systems and methods are disclosed, including maintaining an error recovery data structure for a set of codewords (CWs) in a storage system, the error recovery data structure storing indications that specific CWs are correctable or not correctable by specific error handing (EH) steps of a set of multiple EH steps, and determine an order of EH steps for the storage system based on the error recovery data structure. Maintaining the error recovery data structure can include determining if each CW of the set of CWs is correctable by a specific EH step, storing indications of CWs determined correctable by the specific EH step in the error recovery data structure, and, in response to determining that one or more CW in the set of CWs are not indicated as correctable in the error recovery data structure, incrementing the specific EH step.