中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

69 records (took 0.019 seconds)

    Memory arrays and methods used in forming a memory array
    53.
    发明授权
    Memory arrays and methods used in forming a memory array 有权

    公开(公告)号：US10748922B2

    公开(公告)日：2020-08-18

    申请号：US16203200

    申请日：2018-11-28

    Applicant: Micron Technology, Inc.

    Inventor： Collin Howder ,  Rita J. Klein

    IPC: H01L27/11582 ,  G06F3/06 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11524

    Abstract: A memory array comprises a vertical stack comprising alternating insulative tiers and wordline tiers. The wordline tiers comprise gate regions of individual memory cells. The gate regions individually comprise part of a wordline in individual of the wordline tiers. Channel material extends elevationally through the insulative tiers and the wordline tiers. The individual memory cells comprise a memory structure laterally between the gate region and the channel material. Individual of the wordlines comprise laterally-outer longitudinal-edge portions and a respective laterally-inner portion laterally adjacent individual of the laterally-outer longitudinal-edge portions. The individual laterally-outer longitudinal-edge portions project upwardly and downwardly relative to its laterally-adjacent laterally-inner portion. Methods are disclosed.

    Methods of Forming Metal Silicide-Comprising Material and Methods of Forming Metal Silicide-Comprising Contacts
    54.
    发明申请
    Methods of Forming Metal Silicide-Comprising Material and Methods of Forming Metal Silicide-Comprising Contacts 有权
    形成金属硅化物的方法及其形成金属硅化物的方法

    公开(公告)号：US20140134816A1

    公开(公告)日：2014-05-15

    申请号：US14157192

    申请日：2014-01-16

    Applicant: Micron Technology, Inc.

    Inventor： David H. Wells ,  John Mark Meldrim ,  Rita J. Klein

    IPC: H01L21/28 ,  H01L21/283

    CPC classification number: H01L21/28097 ,  H01L21/283 ,  H01L21/28518 ,  H01L21/32134 ,  H01L21/32139

    Abstract: A method of forming metal silicide-comprising material includes forming a substrate which includes a first stack having second metal over first metal over silicon and a second stack having second metal over silicon. The first and second metals are of different compositions. The substrate is subjected to conditions which react the second metal with the silicon in the second stack to form metal silicide-comprising material from the second stack. The first metal between the second metal and the silicon in the first stack precludes formation of a silicide comprising the second metal and silicon from the first stack. After forming the metal silicide-comprising material, the first metal, the second metal and the metal silicide-comprising material are subjected to an etching chemistry that etches at least some remaining of the first and second metals from the substrate selectively relative to the metal silicide-comprising material.

    Abstract translation: 一种形成含金属硅化物的材料的方法包括形成衬底，该衬底包括具有超过硅的第一金属上的第二金属的第一堆叠和在硅上的第二金属的第二叠层。 第一和第二种金属具有不同的组成。 基板经受使第二金属与第二堆叠中的硅反应以形成来自第二堆叠的含金属硅化物的材料的条件。 第一堆叠中的第二金属和硅之间的第一金属阻止从第一堆叠形成包括第二金属和硅的硅化物。 在形成含金属硅化物的材料之后，对第一金属，第二金属和含金属硅化物的材料进行蚀刻化学，从而选择性地相对于金属硅化物从衬底中蚀刻至少一些剩余的第一和第二金属 令人惊奇的材料。

    Transistor And Memory Circuitry Comprising Strings Of Memory Cells
    59.
    发明申请
    Transistor And Memory Circuitry Comprising Strings Of Memory Cells 有权

    公开(公告)号：US20230016742A1

    公开(公告)日：2023-01-19

    申请号：US17375602

    申请日：2021-07-14

    Applicant: Micron Technology, Inc.

    Inventor： Daniel Billingsley ,  Jordan D. Greenlee ,  Yongjun Jeff Hu ,  Rita J. Klein ,  Everett A. McTeer

    IPC: H01L29/51 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/788 ,  H01L29/792

    Abstract: Memory circuitry comprising strings of memory cells comprises a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings extend through the insulative tiers and the conductive tiers. Charge-passage material is in the conductive tiers laterally-outward of the channel-material strings. Storage material is in the conductive tiers laterally-outward of the charge-passage material. At least one of AlOq, ZrOq, and HfOq is in the conductive tiers laterally-outward of the storage material. At least one of (a) and (b) is in the conductive tiers laterally-outward of the at least one of AlOq, ZrOq, and HfOq, where, (a): MoOxNy, where each of “x” and “y” is from 0 to 4.0; and (b): MoMz, where “M” is at least one of W, a Group 7 metal, and a Group 8 metal; “z” being greater than 0 and less than 1.0. Metal material is in the conductive tiers laterally-outward of the at least one of the (a) and the (b). Memory cells are in individual of the conductive tiers. The memory cells individually comprise the channel material of individual of the channel-material strings, the storage material, the at least one of AlOq, ZrOq, and HfOq, the at least one of the (a) and the (b), and the metal material. Other embodiments are disclosed.

Patent Agency Ranking