公开(公告)号：US10191746B2

公开(公告)日：2019-01-29

申请号：US14360284

申请日：2011-11-22

Applicant: Mohammad Abdallah

Inventor： Mohammad Abdallah

IPC: G06F9/30 ,  G06F9/38

Abstract: A method for accelerating code optimization a microprocessor. The method includes fetching an incoming microinstruction sequence using an instruction fetch component and transferring the fetched macroinstructions to a decoding component for decoding into microinstructions. Optimization processing is performed by reordering the microinstruction sequence into an optimized microinstruction sequence comprising a plurality of dependent code groups. The plurality of dependent code groups are then output to a plurality of engines of the microprocessor for execution in parallel. A copy of the optimized microinstruction sequence is stored into a sequence cache for subsequent use upon a subsequent hit optimized microinstruction sequence.

公开(公告)号：US09842005B2

公开(公告)日：2017-12-12

申请号：US13428438

申请日：2012-03-23

Applicant: Mohammad Abdallah

Inventor： Mohammad Abdallah

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  G06F12/08 ,  G06F13/16 ,  G06F12/0846

CPC classification number: G06F9/5077 ,  G06F9/30043 ,  G06F9/30123 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/5016 ,  G06F9/505 ,  G06F12/0848 ,  G06F13/1657 ,  G06F2212/282

Abstract: A system for executing instructions using a plurality of register file segments for a processor. The system includes a global front end scheduler for receiving an incoming instruction sequence, wherein the global front end scheduler partitions the incoming instruction sequence into a plurality of code blocks of instructions and generates a plurality of inheritance vectors describing interdependencies between instructions of the code blocks. The system further includes a plurality of virtual cores of the processor coupled to receive code blocks allocated by the global front end scheduler, wherein each virtual core comprises a respective subset of resources of a plurality of partitionable engines, wherein the code blocks are executed by using the partitionable engines in accordance with a virtual core mode and in accordance with the respective inheritance vectors. A plurality register file segments are coupled to the partitionable engines for providing data storage.

公开(公告)号：US09710387B2

公开(公告)日：2017-07-18

申请号：US13359767

申请日：2012-01-27

Applicant: Mohammad Abdallah

Inventor： Mohammad Abdallah

IPC: G06F12/08 ,  G06F12/0875 ,  G06F9/45 ,  G06F9/30 ,  G06F9/32 ,  G06F9/38

CPC classification number: G06F9/30174 ,  G06F8/52 ,  G06F9/30058 ,  G06F9/322 ,  G06F9/3802 ,  G06F9/3808 ,  G06F12/0875 ,  G06F2212/151 ,  G06F2212/452

Abstract: A method for translating instructions for a processor. The method includes accessing a plurality of guest instructions that comprise multiple guest branch instructions, and assembling the plurality of guest instructions into a guest instruction block. The guest instruction block is converted into a corresponding native conversion block. The native conversion block is stored into a native cache. A mapping of the guest instruction block to corresponding native conversion block is stored in a conversion look aside buffer. Upon a subsequent request for a guest instruction, the conversion look aside buffer is indexed to determine whether a hit occurred, wherein the mapping indicates whether the guest instruction has a corresponding converted native instruction in the native cache. The converted native instruction is forwarded for execution in response to the hit.

公开(公告)号：US09229873B2

公开(公告)日：2016-01-05

申请号：US13561570

申请日：2012-07-30

Applicant: Karthikeyan Avudaiyappan ,  Mohammad Abdallah

Inventor： Karthikeyan Avudaiyappan ,  Mohammad Abdallah

IPC: G06F12/08

CPC classification number: G06F12/0846 ,  G06F12/0848 ,  G06F12/0895 ,  G06F2212/1021 ,  G06F2212/6082

Abstract: Systems and methods for supporting a plurality of load and store accesses of a cache are disclosed. Responsive to a request of a plurality of requests to access a block of a plurality of blocks of a load cache, the block of the load cache and a logically and physically paired block of a store coalescing cache are accessed in parallel. The data that is accessed from the block of the load cache is overwritten by the data that is accessed from the block of the store coalescing cache by merging on a per byte basis. Access is provided to the merged data.

Abstract translation: 公开了用于支持多个加载和存储高速缓存的访问的系统和方法。 响应于访问加载高速缓存的多个块的块的多个请求的请求，并行地访问加载高速缓存块和存储合并高速缓存的逻辑和物理配对块。 从加载缓存的块访问的数据被通过以每个字节为单位的合并而从存储合并缓存的块中访问的数据覆盖。 访问被提供给合并的数据。

公开(公告)号：US20150286576A1

公开(公告)日：2015-10-08

申请号：US14385968

申请日：2011-12-16

Applicant: Karthikeyan Avudaiyappan ,  Mohammad Abdallah

Inventor： Karthikeyan Avudaiyappan ,  Mohammad Abdallah

IPC: G06F12/08

CPC classification number: G06F12/0897 ,  G06F12/0859 ,  G06F12/0891 ,  G06F12/124 ,  G06F12/126 ,  G06F2212/1008 ,  G06F2212/152 ,  G06F2212/251 ,  G06F2212/301

Abstract: Cache replacement policy. In accordance with a first embodiment of the present invention, an apparatus comprises a queue memory structure configured to queue cache requests that miss a second cache after missing a first cache. The apparatus comprises additional memory associated with the queue memory structure is configured to record an evict way of the cache requests for the cache. The apparatus may be further configured to lock the evict way recorded in the additional memory, for example, to prevent reuse of the evict way. The apparatus may be further configured to unlock the evict way responsive to a fill from the second cache to the cache. The additional memory may be a component of a higher level cache.

Abstract translation: 缓存替换策略。 根据本发明的第一实施例，一种装置包括队列存储器结构，其被配置为对缺少第一高速缓存之后错过第二高速缓存的高速缓存请求进行排队。 所述装置包括与所述队列存储器结构相关联的附加存储器，被配置为记录所述高速缓存的高速缓存请求的逐出方式。 该装置还可以被配置为锁定记录在附加存储器中的驱逐方式，例如以防止重新使用驱逐方式。 该装置还可以被配置为响应于从第二高速缓存到高速缓存的填充来解锁驱逐方式。 附加存储器可以是较高级别高速缓存的组件。

公开(公告)号：US08930674B2

公开(公告)日：2015-01-06

申请号：US13414456

申请日：2012-03-07

Applicant: Karthikeyan Avudaiyappan ,  Mohammad Abdallah

Inventor： Karthikeyan Avudaiyappan ,  Mohammad Abdallah

IPC: G06F13/20

CPC classification number: G06F12/1027 ,  G06F12/0802 ,  G06F12/0875 ,  G06F12/1054 ,  G06F12/1063 ,  G06F2212/1016 ,  G06F2212/1021 ,  G06F2212/152 ,  G06F2212/608 ,  G06F2212/651 ,  G06F2212/652 ,  G06F2212/657 ,  G06F2212/681 ,  G06F2212/684

Abstract: Systems and methods for accessing a unified translation lookaside buffer (TLB) are disclosed. A method includes receiving an indicator of a level one translation lookaside buffer (L1TLB) miss corresponding to a request for a virtual address to physical address translation, searching a cache that includes virtual addresses and page sizes that correspond to translation table entries (TTEs) that have been evicted from the L1TLB, where a page size is identified, and searching a second level TLB and identifying a physical address that is contained in the second level TLB. Access is provided to the identified physical address.

Abstract translation: 公开了用于访问统一翻译后备缓冲器（TLB）的系统和方法。 一种方法包括：接收与虚拟地址到物理地址转换的请求相对应的一级转换后备缓冲器（L1TLB）未命中的指示符，搜索包括虚拟地址的高速缓存和对应于转换表条目（TTE）的页面大小， 已经被从L1TLB逐出，其中标识了页面大小，并且搜索第二级TLB并且识别包含在第二级TLB中的物理地址。 访问被提供给所识别的物理地址。

公开(公告)号：US20140108729A1

公开(公告)日：2014-04-17

申请号：US13649505

申请日：2012-10-11

Applicant: Karthikeyan Avudaiyappan ,  Mohammad Abdallah

Inventor： Karthikeyan Avudaiyappan ,  Mohammad Abdallah

IPC: G06F12/08

CPC classification number: G06F9/30043 ,  G06F9/3842 ,  G06F9/3861 ,  G06F12/0215 ,  G06F12/0862 ,  G06F12/0875 ,  G06F2212/452

Abstract: Systems and methods for load canceling in a processor that is connected to an external interconnect fabric are disclosed. As a part of a method for load canceling in a processor that is connected to an external bus, and responsive to a flush request and a corresponding cancellation of pending speculative loads from a load queue, a type of one or more of the pending speculative loads that are positioned in the instruction pipeline external to the processor, is converted from load to prefetch. Data corresponding to one or more of the pending speculative loads that are positioned in the instruction pipeline external to the processor is accessed and returned to cache as prefetch data. The prefetch data is retired in a cache location of the processor.

Abstract translation: 公开了在连接到外部互连结构的处理器中用于负载消除的系统和方法。 作为在连接到外部总线的处理器中的负载消除的方法的一部分，并且响应于刷新请求以及来自加载队列的等待的推测负载的相应取消，一种或多种待处理的投机负载 位于处理器外部的指令流水线中，从负载转换为预取。 对应于位于处理器外部的指令流水线中的一个或多个未决投机负载的数据被访问并作为预取数据返回到高速缓存。 预取数据在处理器的高速缓存位置中退出。

公开(公告)号：US20140032856A1

公开(公告)日：2014-01-30

申请号：US13561441

申请日：2012-07-30

Applicant: Karthikeyan Avudaiyappan ,  Mohammad Abdallah

Inventor： Karthikeyan Avudaiyappan ,  Mohammad Abdallah

IPC: G06F12/08

CPC classification number: G06F12/0811 ,  G06F12/0804 ,  G06F12/0815 ,  G06F12/0897 ,  G06F12/12 ,  G06F2212/1016 ,  G06F2212/1032 ,  G06F2212/1048 ,  G06F2212/283 ,  G06F2212/608

Abstract: A method for maintaining the coherency of a store coalescing cache and a load cache is disclosed. As a part of the method, responsive to a write-back of an entry from a level one store coalescing cache to a level two cache, the entry is written into the level two cache and into the level one load cache. The writing of the entry into the level two cache and into the level one load cache is executed at the speed of access of the level two cache.

Abstract translation: 公开了一种用于维持存储合并高速缓存和加载高速缓存的一致性的方法。 作为该方法的一部分，响应于从一级存储器将并行缓存合并到二级高速缓存的条目的写入，该条目被写入二级高速缓存并进入一级加载高速缓存。 将条目写入二级缓存并进入一级加载缓存以二级缓存的访问速度执行。

公开(公告)号：US20140032846A1

公开(公告)日：2014-01-30

申请号：US13561570

申请日：2012-07-30

Applicant: Karthikeyan Avudaiyappan ,  Mohammad Abdallah

Inventor： Karthikeyan Avudaiyappan ,  Mohammad Abdallah

IPC: G06F12/08

CPC classification number: G06F12/0846 ,  G06F12/0848 ,  G06F12/0895 ,  G06F2212/1021 ,  G06F2212/6082

Abstract: Systems and methods for supporting a plurality of load and store accesses of a cache are disclosed. Responsive to a request of a plurality of requests to access a block of a plurality of blocks of a load cache, the block of the load cache and a logically and physically paired block of a store coalescing cache are accessed in parallel. The data that is accessed from the block of the load cache is overwritten by the data that is accessed from the block of the store coalescing cache by merging on a per byte basis. Access is provided to the merged data.

Abstract translation: 公开了用于支持多个加载和存储高速缓存的访问的系统和方法。 响应于访问加载高速缓存的多个块的块的多个请求的请求，并行地访问加载高速缓存块和存储合并高速缓存的逻辑和物理配对块。 从加载缓存的块访问的数据被通过以每个字节为单位的合并而从存储合并缓存的块中访问的数据覆盖。 访问被提供给合并的数据。

公开(公告)号：US20140032844A1

公开(公告)日：2014-01-30

申请号：US13561491

申请日：2012-07-30

Applicant: Karthikeyan Avudaiyappan ,  Mohammad Abdallah

Inventor： Karthikeyan Avudaiyappan ,  Mohammad Abdallah

IPC: G06F12/08

CPC classification number: G06F12/128 ,  G06F12/0802 ,  G06F12/0808 ,  G06F12/0811 ,  G06F12/126 ,  G06F2212/283 ,  G06F2212/608 ,  G06F2212/70

Abstract: Systems and methods for flushing a cache with modified data are disclosed. Responsive to a request to flush data from a cache with modified data to a next level cache that does not include the cache with modified data, the cache with modified data is accessed using an index and a way and an address associated with the index and the way is secured. Using the address, the cache with modified data is accessed a second time and an entry that is associated with the address is retrieved from the cache with modified data. The entry is placed into a location of the next level cache.

Abstract translation: 公开了用修改的数据冲洗高速缓存的系统和方法。 响应于将具有修改的数据的缓存中的数据刷新到不包括具有修改的数据的高速缓存的下一级高速缓存的请求，具有修改的数据的高速缓存使用索引和与索引相关联的方式和地址来访问， 方式是有保障的。 使用该地址，第二次访问具有修改数据的高速缓存，并且使用修改的数据从缓存中检索与该地址相关联的条目。 该条目被放置在下一级缓存的位置。