公开(公告)号：US07910433B2

公开(公告)日：2011-03-22

申请号：US12478538

申请日：2009-06-04

申请人： Young-Chul Jang ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Jae-Hoon Jang

发明人： Young-Chul Jang ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Jae-Hoon Jang

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/84

CPC分类号： H01L27/105 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551

摘要： A nonvolatile memory device includes a semiconductor substrate having a first well region of a first conductivity type, and at least one semiconductor layer formed on the semiconductor substrate. A first cell array is formed on the semiconductor substrate, and a second cell array formed on the semiconductor layer. The semiconductor layer includes a second well region of the first conductivity type having a doping concentration greater than a doping concentration of the first well region of the first conductivity type. As the doping concentration of the second well region is increased, a resistance difference may be reduced between the first and second well regions.

摘要翻译： 非易失性存储器件包括具有第一导电类型的第一阱区和形成在半导体衬底上的至少一个半导体层的半导体衬底。 第一单元阵列形成在半导体衬底上，第二单元阵列形成在半导体层上。 半导体层包括第一导电类型的第二阱区，其具有大于第一导电类型的第一阱区的掺杂浓度的掺杂浓度。 随着第二阱区域的掺杂浓度增加，可以在第一和第二阱区域之间减小电阻差。

公开(公告)号：US07692970B2

公开(公告)日：2010-04-06

申请号：US11943887

申请日：2007-11-21

申请人： Ki-Tae Park ,  Yong-Seok Kim ,  Ki-Nam Kim ,  Yeong-Taek Lee

发明人： Ki-Tae Park ,  Yong-Seok Kim ,  Ki-Nam Kim ,  Yeong-Taek Lee

IPC分类号： G11C11/34

CPC分类号： G11C16/344 ,  G11C16/3454

摘要： Disclosed is a method of verifying a programmed condition of a flash memory device, being comprised of: determining a level of an additional verifying voltage in response to the number of programming/erasing cycles of memory cells; conducting a verifying operation to programmed memory cells with an initial verifying voltage lower than the additional verifying voltage; and selectively conducting an additional verifying operation with the additional verifying voltage to the program-verified memory cells in response to the number of programming/erasing cycles.

摘要翻译： 公开了一种验证闪速存储器件的编程状态的方法，其包括：响应于存储器单元的编程/擦除循环的数量确定额外的验证电压的电平; 对初始验证电压低于附加验证电压的程序存储单元执行验证操作; 以及响应于所述编程/擦除周期的数量，选择性地对所述经过程序验证的存储器单元执行附加验证电压的附加验证操作。

公开(公告)号：US07675783B2

公开(公告)日：2010-03-09

申请号：US12035732

申请日：2008-02-22

申请人： Ki-Tae Park ,  Ki-Nam Kim ,  Yeong-Taek Lee

发明人： Ki-Tae Park ,  Ki-Nam Kim ,  Yeong-Taek Lee

IPC分类号： G11C16/04

CPC分类号： G11C11/5621 ,  G11C16/10 ,  G11C16/30 ,  G11C16/3454

摘要： Provided are a nonvolatile memory device and a driving method thereof. In the method of driving a nonvolatile memory device, a structural shape and position of a memory cell to be driven is determined, and then the memory cell is driven with an optimized operating condition according to a distribution of the memory cell using a determination result.

摘要翻译： 提供一种非易失性存储装置及其驱动方法。 在驱动非易失性存储器件的方法中，确定要驱动的存储单元的结构形状和位置，然后使用确定结果根据存储单元的分布以优化的操作条件驱动存储单元。

公开(公告)号：US07551480B2

公开(公告)日：2009-06-23

申请号：US11637791

申请日：2006-12-13

申请人： Ki-Tae Park ,  Ki-Nam Kim ,  Yeong-Taek Lee

发明人： Ki-Tae Park ,  Ki-Nam Kim ,  Yeong-Taek Lee

IPC分类号： G11C11/34

CPC分类号： G11C16/0408 ,  G11C11/5621 ,  G11C16/0483 ,  G11C16/10 ,  G11C2211/5641 ,  G11C2211/5642

摘要： A flash memory device comprises a plurality of memory blocks. A selected memory block among the plurality of memory blocks includes 2n pages of data. The selected memory block includes different types of memory cells capable of storing different numbers of bits.

摘要翻译： 闪存器件包括多个存储器块。 多个存储块中选择的存储块包括2n页的数据。 所选存储块包括能够存储不同位数的不同类型的存储单元。

公开(公告)号：US07411241B2

公开(公告)日：2008-08-12

申请号：US11325964

申请日：2006-01-05

申请人： Ki-Nam Kim ,  Yun-Gi Kim

发明人： Ki-Nam Kim ,  Yun-Gi Kim

IPC分类号： H01L27/108

CPC分类号： H01L29/78642 ,  B82Y10/00 ,  H01L27/1085 ,  H01L27/10873 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/78681 ,  H01L29/7869 ,  Y10S977/938

摘要： A vertical type nanotube semiconductor device including a nanotube bit line, disposed on a substrate and in parallel with the substrate and composed of a nanotube with a conductive property, and a nanotube pole connected to the bit line vertically to the substrate and provides a channel through which carriers migrate. By manufacturing the semiconductor device using the bit line composed of the nanotube, cutoff of an electrical connection of the bit line is prevented and an integration density of the semiconductor device can be improved.

摘要翻译： 一种垂直型纳米管半导体器件，包括：纳米管位线，其设置在基板上并且与所述基板并联并且由具有导电性质的纳米管构成，并且纳米管极与所述位线垂直地连接到所述基板，并且提供通道 哪些运营商迁移。 通过使用由纳米管构成的位线制造半导体器件，防止了位线的电连接的切断，并且可以提高半导体器件的集成密度。

公开(公告)号：US20080160693A1

公开(公告)日：2008-07-03

申请号：US11945477

申请日：2007-11-27

申请人： Jae-Hwang Sim ,  Yong-Sik Yim ,  Ki-Nam Kim ,  Jae-Kwan Park

发明人： Jae-Hwang Sim ,  Yong-Sik Yim ,  Ki-Nam Kim ,  Jae-Kwan Park

IPC分类号： H01L21/8247

CPC分类号： H01L27/11524 ,  H01L27/115 ,  H01L27/11521 ,  Y10S438/954

摘要： A method of forming a non-volatile memory device includes forming first mask patterns, which can have relatively large distances therebetween. A distance regulating layer is formed that conformally covers the first mask patterns. Second mask patterns are formed in grooves on the distance regulating layer between the first mask patterns.

摘要翻译： 形成非易失性存储器件的方法包括形成第一掩模图案，它们之间的距离可以相对较大。 形成保形地覆盖第一掩模图案的距离调节层。 在第一掩模图案之间的距离调节层的凹槽中形成第二掩模图案。

公开(公告)号：US20080094914A1

公开(公告)日：2008-04-24

申请号：US11616411

申请日：2006-12-27

申请人： Ki-Tae Park ,  Ki-Nam Kim ,  Yeong-Taek Lee

发明人： Ki-Tae Park ,  Ki-Nam Kim ,  Yeong-Taek Lee

IPC分类号： G11C16/04

CPC分类号： G11C16/349 ,  G11C16/3495

摘要： Methods for setting a read voltage in a memory system which comprises a flash memory device and a memory controller for controlling the flash memory device, comprise sequentially varying a distribution read voltage to read page data from the flash memory device; constituting a distribution table having a data bit number and a distribution read voltage, the data bit number indicating an erase state among the page data respectively read from the flash memory device and the distribution read voltage corresponding to the read page data; detecting distribution read voltages corresponding to data bit numbers each indicating maximum points of possible cell states of a memory cell, based on the distribution table; and defining new read voltages based on the detected distribution read voltages.

摘要翻译： 包括闪速存储器装置和用于控制闪速存储器件的存储器控​​制器的存储器系统中设置读取电压的方法包括顺序地改变分配读取电压以从闪速存储器装置读取页面数据; 构成具有数据位数和分布读电压的分布表，分别表示从闪存器件分别读取的页数据中的擦除状态的数据位数和与读页数据相对应的分布读电压; 基于分布表，检测对应于每个表示存储器单元的可能单元状态的最大点的数据位数的分布读取电压; 以及基于检测到的分布读取电压来定义新的读取电压。

公开(公告)号：US07344940B2

公开(公告)日：2008-03-18

申请号：US10967936

申请日：2004-10-19

申请人： Hyun-Ho Kim ,  Ki-Nam Kim

发明人： Hyun-Ho Kim ,  Ki-Nam Kim

IPC分类号： H01L21/8242

CPC分类号： H01L27/11502 ,  H01L23/522 ,  H01L27/11507 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

摘要： Integrated circuit ferroelectric memory devices are provided that include an integrated circuit transistor. The memory device further includes a ferroelectric capacitor on the integrated circuit transistor. The ferroelectric capacitor includes a first electrode adjacent the transistor, a second electrode remote from the transistor and a ferroelectric film therebetween. The memory device further includes a plate line directly on the ferroelectric capacitor. Methods are also provided that include forming a ferroelectric capacitor on the integrated circuit transistor and forming a plate line directly on the ferroelectric capacitor.

摘要翻译： 提供了包括集成电路晶体管的集成电路铁电存储器件。 存储器件还包括集成电路晶体管上的铁电电容器。 铁电电容器包括与晶体管相邻的第一电极，远离晶体管的第二电极和其间的铁电体膜。 存储装置还包括直接在铁电电容器上的板线。 还提供了包括在集成电路晶体管上形成铁电电容器并且在铁电电容器上直接形成板线的方法。

公开(公告)号：US20070165455A1

公开(公告)日：2007-07-19

申请号：US11637686

申请日：2006-12-12

申请人： Jae-Kwan Park ,  Ki-Nam Kim ,  Soon-Moon Jung

发明人： Jae-Kwan Park ,  Ki-Nam Kim ,  Soon-Moon Jung

IPC分类号： G11C16/04 ,  H01L21/336 ,  H01L29/788

CPC分类号： H01L27/115 ,  G11C16/0483 ,  H01L27/11568 ,  H01L27/11578

摘要： A NAND-type nonvolatile memory device includes a semiconductor substrate and a first ground selection line and a first string selection line disposed on the substrate in parallel to each other. A plurality of parallel first word lines are interposed on the substrate between the first ground selection line and the first string selection line. A first impurity-doped region is formed in the semiconductor substrate adjacent to the first word lines, the first ground selection line, and the first string selection line. A first interlayer dielectric layer is disposed on the first ground selection line, the first string selection line, the plurality of first word lines, and the semiconductor substrate. An epitaxial contact plug contacts the semiconductor substrate through the first interlayer dielectric layer. A single crystalline semiconductor layer is disposed on the first interlayer dielectric layer that contacts the epitaxial contact plug. A plurality of parallel second word lines is disposed on the single crystalline semiconductor layer. A second impurity-doped region formed in the single crystalline semiconductor layer adjacent to the second word lines. A second interlayer dielectric layer is disposed on the plurality of second word lines and the single crystalline semiconductor layer.

摘要翻译： NAND型非易失性存储器件包括半导体衬底和彼此平行地布置在衬底上的第一接地选择线和第一串选择线。 在第一接地选择线和第一串选择线之间的基板上插入多个平行的第一字线。 在与第一字线，第一地选择线和第一串选择线相邻的半导体衬底中形成第一杂质掺杂区。 第一层间介电层设置在第一接地选择线，第一串选择线，多个第一字线和半导体衬底上。 外延接触插塞通过第一层间介电层与半导体衬底接触。 单晶半导体层设置在与外延接触插塞接触的第一层间电介质层上。 多个平行的第二字线布置在单晶半导体层上。 形成在与第二字线相邻的单晶半导体层中的第二杂质掺杂区。 第二层间介电层设置在多个第二字线和单晶半导体层上。

公开(公告)号：US07164598B2

公开(公告)日：2007-01-16

申请号：US11201495

申请日：2005-08-11

申请人： Won-Cheol Jeong ,  Ki-Nam Kim ,  Hong-Sik Jeong ,  Gi-Tae Jeong ,  Jae-Hyun Park

发明人： Won-Cheol Jeong ,  Ki-Nam Kim ,  Hong-Sik Jeong ,  Gi-Tae Jeong ,  Jae-Hyun Park

IPC分类号： G11C11/00 ,  G11C11/15

CPC分类号： G11C11/16

摘要： Methods are provided for operating a magnetic random access memory device including a memory cell having a magnetic tunnel junction structure on a substrate. In particular, a writing current pulse may be provided through the magnetic tunnel junction structure, and a writing magnetic field pulse may be provided through the magnetic tunnel junction structure. In addition, at least a portion of the writing magnetic field pulse may be overlapping in time with respect to at least a portion of the writing current pulse, and at least a portion of the writing current pulse and/or at least a portion of the writing magnetic field pulse may be non-overlapping in time with respect to the other. Related devices are also discussed.

摘要翻译： 提供了用于操作包括在衬底上具有磁性隧道结结构的存储单元的磁性随机存取存储器件的方法。 特别地，可以通过磁性隧道结结构提供写入电流脉冲，并且可以通过磁性隧道结结构提供写入磁场脉冲。 此外，写入磁场脉冲的至少一部分可以相对于写入电流脉冲的至少一部分在时间上重叠，并且写入电流脉冲的至少一部分和/或至少一部分 写入磁场脉冲可能在时间上相对于另一个不重叠。 还讨论了相关设备。