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335 条记录 (耗时 0.039 秒)

    SEMICONDUCTOR DEVICE
    51.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20120175736A1

    公开(公告)日：2012-07-12

    申请号：US13426014

    申请日：2012-03-21

    申请人： Kenichi Watanabe

    发明人： Kenichi Watanabe

    IPC分类号： H01L29/92 ,  H01L21/02 ,  H01L21/768

    CPC分类号： H01L21/486 ,  H01L23/5223 ,  H01L23/5226 ,  H01L28/40 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A substrate is provided with a first wiring layer 111, an interlayer insulating film 132 on the first wiring layer 111, a hole 112A formed in the interlayer insulating film, a first metal layer 112 covering the hole 112A, a second metal layer 113 formed in the hole 112A, a dielectric insulating film 135 on the first metal layer 112, and second wiring layers 114-116 on the dielectric insulating film 135, wherein the first metal layer 112 constitutes at least part of the lower electrode, an area, facing the lower electrode, of the second wiring layers 114-116 constitutes the upper electrode, and a capacitor 160 is constructed of the lower electrode, the dielectric insulating film 135 and the upper electrode P1.

    摘要翻译： 基板在第一布线层111上设置有第一布线层111，层间绝缘膜132，形成在层间绝缘膜中的孔112A，覆盖孔112A的第一金属层112，形成在第一布线层111上的第二金属层113 孔112A，第一金属层112上的介电绝缘膜135和介电绝缘膜135上的第二布线层114-116，其中第一金属层112构成下电极的至少一部分，面向 第二布线层114-116的下电极构成上电极，电容器160由下电极，电介质绝缘膜135和上电极P1构成。

    SEMICONDUCTOR DEVICE
    52.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20120149190A1

    公开(公告)日：2012-06-14

    申请号：US13398254

    申请日：2012-02-16

    申请人： Kenichi Watanabe ,  Nobuhiro Misawa ,  Satoshi Otsuka

    发明人： Kenichi Watanabe ,  Nobuhiro Misawa ,  Satoshi Otsuka

    IPC分类号： H01L21/768

    CPC分类号： H01L23/562 ,  H01L23/3192 ,  H01L23/564 ,  H01L24/05 ,  H01L2224/02166 ,  H01L2224/05567 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2224/05552

    摘要： A method of manufacturing a semiconductor device, including: forming a moisture resistant ring surrounding a multilayer interconnection structure in a layered body formed of stacked layers of a plurality of interlayer insulating films lower in dielectric constant than a SiO2 film and including the multilayer interconnection structure; forming a groove in the layered body between the moisture resistant ring and a scribe line, the groove reaching a surface of a semiconductor substrate; forming a film including Si and C as principal components and covering sidewall surfaces and a bottom surface of the groove; and forming a protection film on the film along the sidewall surfaces and the bottom surface of the groove.

    摘要翻译： 一种制造半导体器件的方法，包括：在由SiO 2膜介电常数低于介电常数的多个层间绝缘膜的叠层形成的层叠体中形成包围多层互连结构的防潮环，并且包括所述多层互连结构; 在所述层叠体之间在所述防潮环和划线之间形成凹槽，所述凹槽到达半导体衬底的表面; 形成包括Si和C作为主要成分并覆盖所述槽的侧壁表面和底表面的膜; 以及沿着所述凹槽的侧壁表面和所述底表面在所述膜上形成保护膜。

    Method for manufacturing semiconductor device
    53.
    发明授权
    Method for manufacturing semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US08143153B2

    公开(公告)日：2012-03-27

    申请号：US13075463

    申请日：2011-03-30

    申请人： Kenichi Watanabe ,  Nobuhiro Misawa ,  Satoshi Otsuka

    发明人： Kenichi Watanabe ,  Nobuhiro Misawa ,  Satoshi Otsuka

    IPC分类号： H01L21/44 ,  H01L21/4763 ,  H01L21/311

    CPC分类号： H01L23/562 ,  H01L23/3192 ,  H01L23/564 ,  H01L24/05 ,  H01L2224/02166 ,  H01L2224/05567 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2224/05552

    摘要： A method of manufacturing a semiconductor device, including: forming a moisture resistant ring surrounding a multilayer interconnection structure in a layered body formed of stacked layers of a plurality of interlayer insulating films lower in dielectric constant than a SiO2 film and including the multilayer interconnection structure; forming a groove in the layered body between the moisture resistant ring and a scribe line, the groove reaching a surface of a semiconductor substrate; forming a film including Si and C as principal components and covering sidewall surfaces and a bottom surface of the groove; and forming a protection film on the film along the sidewall surfaces and the bottom surface of the groove.

    摘要翻译： 一种制造半导体器件的方法，包括：在由SiO 2膜介电常数低于介电常数的多个层间绝缘膜的叠层形成的层叠体中形成包围多层互连结构的防潮环，并且包括所述多层互连结构; 在所述层叠体之间在所述防潮环和划线之间形成凹槽，所述凹槽到达半导体衬底的表面; 形成包括Si和C作为主要成分并覆盖所述槽的侧壁表面和底表面的膜; 以及沿着所述凹槽的侧壁表面和所述底表面在所述膜上形成保护膜。

    Embedded wiring in copper damascene with void suppressing structure
    56.
    发明授权
    Embedded wiring in copper damascene with void suppressing structure 有权
    铜镶嵌嵌入式布线，具有空隙抑制结构

    公开(公告)号：US07923806B2

    公开(公告)日：2011-04-12

    申请号：US11084014

    申请日：2005-03-21

    申请人： Kenichi Watanabe

    发明人： Kenichi Watanabe

    IPC分类号： H01L29/00

    CPC分类号： H01L21/76877 ,  H01L21/76805 ,  H01L21/76847 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device capable of restricting a void growth in a copper wiring. The semiconductor device comprises a semiconductor substrate, an insulation layer formed above the semiconductor substrate, a barrier metal layer that is a first damascene wiring buried in the insulation layer, defines the bottom face and the side faces, and also defines a first hollow part at the inner side, a copper wiring layer disposed in the first hollow part and defining a second hollow part at the inner side, a first damascene wiring disposed in the second hollow part and containing an auxiliary barrier metal layer separated from the barrier metal layer, and an insulating copper diffusion preventing film disposed on the first damascene wiring and the insulation layer.

    摘要翻译： 一种能够限制铜布线中的空隙生长的半导体器件。 半导体器件包括半导体衬底，形成在半导体衬底上的绝缘层，作为掩埋在绝缘层中的第一镶嵌布线的阻挡金属层，限定底面和侧面，并且还限定第一中空部分 内侧，设置在第一中空部分中并在内侧限定第二中空部分的铜布线层，设置在第二中空部分中并且包含与阻挡金属层分离的辅助阻挡金属层的第一镶嵌布线，以及 设置在第一镶嵌布线和绝缘层上的绝缘铜扩散防止膜。

    Chip Pickup Method and Chip Pickup Apparatus
    57.
    发明申请
    Chip Pickup Method and Chip Pickup Apparatus 审中-公开
    芯片拾取方法和芯片拾取装置

    公开(公告)号：US20100289283A1

    公开(公告)日：2010-11-18

    申请号：US12445689

    申请日：2007-10-12

    申请人： Kenichi Watanabe ,  Takeshi Segawa ,  Hironobu Fujimoto

    发明人： Kenichi Watanabe ,  Takeshi Segawa ,  Hironobu Fujimoto

    IPC分类号： B25J15/06 ,  H01L21/683

    CPC分类号： H01L21/67132 ,  H01L21/6838

    摘要： A method is provided for picking up a chip 13 from a fixing jig 3 to which the chip 13 is fixed. The fixing jig 3 consists of a jig base 30 having a plurality of protrusions 36 on one side and a sidewall 35 having a height almost equivalent to that of the protrusion 36 at the outer circumference of the one side, and an contact layer 31 that is laminated on the surface of the jig base 30 having the protrusions 36 and that is bonded on the upper surface of the sidewall 35. A section space 37 is formed on the surface of the jig base 30 having the protrusions by the contact layer 31, the protrusions 36 and the sidewall 35, and at least one through hole 38 penetrating the outside and the section space 37 is provided in the jig base 30. The pickup method comprises the steps of fixing a chip, deforming the contact layer 31 by suctioning of air in the section space 37 through the through hole 38, and picking up the chip 13 completely from the contact layer 31 by suctioning the chip 13 from the upper surface side of the chip 13 by means of a suction collet 70.

    摘要翻译： 提供了一种用于从固定夹具3拾取芯片13的方法，固定夹具3固定芯片13。 固定夹具3由在一侧具有多个突起36的夹具基座30和具有与一侧的外周的突起36的高度几乎相同的高度的侧壁35以及接触层31 层压在具有突起36的夹具基座30的表面上并且接合在侧壁35的上表面上。在具有突起的夹具基座30的表面上通过接触层31形成截面空间37， 突起36和侧壁35以及贯穿外部的至少一个通孔38，并且在夹具基座30中设置有截面空间37.拾取方法包括如下步骤：固定芯片，通过抽吸空气使接触层31变形 在截面空间37中通过通孔38，并且通过吸力夹头70从芯片13的上表面侧抽吸芯片13，完全从接触层31拾取芯片13。

    SEMICONDUCTOR DEVICE
    58.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20100219508A1

    公开(公告)日：2010-09-02

    申请号：US12702729

    申请日：2010-02-09

    申请人： Kenichi Watanabe

    发明人： Kenichi Watanabe

    IPC分类号： H01L23/58 ,  G03F7/20

    CPC分类号： H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device includes a semiconductor substrate on which an internal circuit is formed in a central position an insulating layer formed over the semiconductor substrate, and a moisture-resistant ring formed by a metal plug embedded in the insulating layer, the moisture-resistant ring surrounding the internal circuit, the moisture-resistant ring extending over the semiconductor substrate in a shape, the moisture-resistant ring including a first extending portion linearly extending in a first direction in parallel to the surface of the semiconductor substrate, a vertical portion connected to the first extending portion extending in a second direction orthogonal to the first extending portion, and a second extending portion orthogonal to the vertical portion and parallel to the surface of the semiconductor substrate, the second extending portion spaced apart from the first extending portion, the second extending portion crossing the vertical portion.

    摘要翻译： 半导体器件包括半导体衬底，其中在内部电路在中心位置形成在半导体衬底上形成的绝缘层，以及由嵌入绝缘层中的金属插塞形成的防潮环，围绕 所述内部电路，所述防湿环形成为在所述半导体基板上延伸的形状，所述防湿环包括与所述半导体基板的表面平行的第一方向上直线延伸的第一延伸部， 第一延伸部分，其在与第一延伸部分正交的第二方向上延伸;以及第二延伸部分，其垂直于垂直部分并平行于半导体基板的表面，第二延伸部分与第一延伸部分间隔开，第二延伸部分 横穿垂直部分的部分。

    Semiconductor device
    59.
    发明申请
    Semiconductor device 有权

    公开(公告)号：US20090294905A1

    公开(公告)日：2009-12-03

    申请号：US12461136

    申请日：2009-08-03

    申请人： Kenichi Watanabe

    发明人： Kenichi Watanabe

    IPC分类号： H01L29/92 ,  H01L21/768 ,  H01L21/02

    CPC分类号： H01L21/486 ,  H01L23/5223 ,  H01L23/5226 ,  H01L28/40 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A substrate is provided with a first wiring layer 111, an interlayer insulating film 132 on the first wiring layer 111, a hole 112A formed in the interlayer insulating film, a first metal layer 112 covering the hole 112A, a second metal layer 113 formed in the hole 112A, a dielectric insulating film 135 on the first metal layer 112, and second wiring layers 114-116 on the dielectric insulating film 135, wherein the first metal layer 112 constitutes at least part of the lower electrode, an area, facing the lower electrode, of the second wiring layers 114-116 constitutes the upper electrode, and a capacitor 160 is constructed of the lower electrode, the dielectric insulating film 135 and the upper electrode P1.

    Semiconductor device
    60.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US07586143B2

    公开(公告)日：2009-09-08

    申请号：US11339701

    申请日：2006-01-26

    申请人： Kenichi Watanabe

    发明人： Kenichi Watanabe

    IPC分类号： H01L27/108

    CPC分类号： H01L21/486 ,  H01L23/5223 ,  H01L23/5226 ,  H01L28/40 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A substrate is provided with a first wiring layer 111, an interlayer insulating film 132 on the first wiring layer 111, a hole 112A formed in the interlayer insulating film, a first metal layer 112 covering the hole 112A, a second metal layer 113 formed in the hole 112A, a dielectric insulating film 135 on the first metal layer 112, and second wiring layers 114-116 on the dielectric insulating film 135, wherein the first metal layer 112 constitutes at least part of the lower electrode, an area, facing the lower electrode, of the second wiring layers 114-116 constitutes the upper electrode, and a capacitor 160 is constructed of the lower electrode, the dielectric insulating film 135 and the upper electrode P1.

    摘要翻译： 基板在第一布线层111上设置有第一布线层111，层间绝缘膜132，形成在层间绝缘膜中的孔112A，覆盖孔112A的第一金属层112，形成在第一布线层111上的第二金属层113 孔112A，第一金属层112上的介电绝缘膜135和介电绝缘膜135上的第二布线层114-116，其中第一金属层112构成下电极的至少一部分，面向 第二布线层114-116的下电极构成上电极，电容器160由下电极，电介质绝缘膜135和上电极P1构成。