公开(公告)号：US09263522B2

公开(公告)日：2016-02-16

申请号：US14100760

申请日：2013-12-09

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  Xia Li ,  PR Chidambaram

IPC: H01L29/15 ,  H01L29/10 ,  H01L29/205 ,  H01L29/66 ,  H01L21/74 ,  H01L29/78

CPC classification number: H01L29/1045 ,  H01L21/743 ,  H01L29/1054 ,  H01L29/1087 ,  H01L29/205 ,  H01L29/66522 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7834 ,  H01L29/7848 ,  H01L29/785

Abstract: An apparatus comprises a substrate. The apparatus also comprises a diffusion barrier formed on a surface of a first region of the substrate. The diffusion barrier is formed using a first material having a first band gap energy. The apparatus further comprises a channel region formed on a surface of the diffusion barrier. The channel region is formed using a second material having a second band gap energy that is lower than the first band gap energy. The apparatus further comprises a back gate contact coupled to the first region of the substrate.

Abstract translation: 一种装置包括基板。 该装置还包括形成在基板的第一区域的表面上的扩散阻挡层。 使用具有第一带隙能量的第一材料形成扩散阻挡层。 该装置还包括形成在扩散阻挡层的表面上的沟道区。 沟道区域使用具有低于第一带隙能量的第二带隙能量的第二材料形成。 该装置还包括耦合到衬底的第一区域的背栅极接触。

公开(公告)号：US09245971B2

公开(公告)日：2016-01-26

申请号：US14040366

申请日：2013-09-27

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  P R Chidambaram ,  John Jianhong Zhu ,  Jihong Choi ,  Da Yang ,  Ravi Mahendra Todi ,  Giridhar Nallapati ,  Chock Hing Gan ,  Ming Cai ,  Samit Sengupta

IPC: H01L29/66 ,  H01L29/778 ,  H01L21/8238

CPC classification number: H01L29/66431 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66621 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/778 ,  H01L29/7834

Abstract: In a particular embodiment, a semiconductor device includes a high mobility channel between a source region and a drain region. The high mobility channel extends substantially a length of a gate. The semiconductor device also includes a doped region extending from the source region or the drain region toward the high mobility channel. A portion of a substrate is positioned between the doped region and the high mobility channel.

Abstract translation: 在特定实施例中，半导体器件包括源极区和漏极区之间的高迁移率沟道。 高迁移率通道基本上延伸了一个门的长度。 半导体器件还包括从源极区域或漏极区域向高迁移率通道延伸的掺杂区域。 衬底的一部分位于掺杂区域和高迁移率通道之间。

公开(公告)号：US09153587B2

公开(公告)日：2015-10-06

申请号：US14659893

申请日：2015-03-17

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Bin Yang ,  Stanley Seungchul Song

IPC: H01L21/336 ,  H01L29/786 ,  H01L27/092 ,  H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L21/8238 ,  H01L21/265 ,  G06F17/50

CPC classification number: H01L27/0924 ,  G06F17/5045 ,  G06F17/5068 ,  H01L21/265 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L29/0607 ,  H01L29/1041 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: An apparatus comprises a substrate and a fin-type semiconductor device extending from the substrate. The fin-type semiconductor device comprises means for providing a first fin-type conduction channel having first and second regions, means for providing a second fin-type conduction channel having a fourth region above a third region, and means for shielding current leakage coupled to at least one of the first region and the third region. The first region has a first doping concentration greater than a second doping concentration of the second region. The first fin-type conduction channel comprises first ion implants implanted into the substrate at a first depth and second ion implants implanted into the substrate at a different depth. The third region has a third doping concentration, and the fourth region has a fourth doping concentration.

Abstract translation: 一种装置包括从衬底延伸的衬底和鳍式半导体器件。 翅片型半导体器件包括用于提供具有第一和第二区域的第一鳍式传导沟道的装置，用于提供具有在第三区域上方的第四区域的第二鳍式传导沟道的装置，以及用于屏蔽漏电耦合到 第一区域和第三区域中的至少一个。 第一区域具有大于第二区域的第二掺杂浓度的第一掺杂浓度。 第一鳍型传导通道包括在第一深度处植入衬底中的第一离子植入物和在不同深度处植入衬底中的第二离子植入物。 第三区域具有第三掺杂浓度，第四区域具有第四掺杂浓度。

公开(公告)号：US20150145592A1

公开(公告)日：2015-05-28

申请号：US14225836

申请日：2014-03-26

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Daeik Daniel Kim ,  Bin Yang ,  Jonghae Kim ,  Daniel Wayne Perry

IPC: H01L29/739 ,  G05F3/16

CPC classification number: H01L29/7393 ,  G05F3/16 ,  H01L27/0705

Abstract: A method includes biasing a first gate voltage to enable unipolar current to flow from a first region of a transistor to a second region of the transistor according to a field-effect transistor (FET)-type operation. The method also includes biasing a body terminal to enable bipolar current to flow from the first region to the second region according to a bipolar junction transistor (BJT)-type operation. The unipolar current flows concurrently with the bipolar current to provide dual mode digital and analog device in complementary metal oxide semiconductor (CMOS) technology.

Abstract translation: 一种方法包括根据场效应晶体管（FET）型操作，偏置第一栅极电压以使单相电流从晶体管的第一区域流过晶体管的第二区域。 该方法还包括偏置主体端子以使得双极电流能够根据双极结型晶体管（BJT）型操作从第一区域流动到第二区域。 单极电流与双极电流同时流动，在互补金属氧化物半导体（CMOS）技术中提供双模数字和模拟器件。

公开(公告)号：US08980708B2

公开(公告)日：2015-03-17

申请号：US13770127

申请日：2013-02-19

Applicant: QUALCOMM Incorporated

Inventor： John J. Zhu ,  Bin Yang ,  P R Chidambaram ,  Lixin Ge ,  Jihong Choi

IPC: H01L21/8244 ,  H01L23/538 ,  H01L27/08 ,  H01L49/02 ,  H01L23/522

CPC classification number: H01L23/538 ,  H01L23/5223 ,  H01L27/0805 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A complementary back end of line (BEOL) capacitor (CBC) structure includes a metal oxide metal (MOM) capacitor structure. The MOM capacitor structure is coupled to a first upper interconnect layer of an interconnect stack of an integrated circuit (IC) device. The MOM capacitor structure includes at least one lower interconnect layer of the interconnect stack. The CBC structure may also include a second upper interconnect layer of the interconnect stack coupled to the MOM capacitor structure. The CBC structure also includes at least one metal insulator metal (MIM) capacitor layer between the first upper interconnect layer and the second upper interconnect layer. In addition, CBC structure may also include a MIM capacitor structure coupled to the MOM capacitor structure. The MIM capacitor structure includes a first capacitor plate having at least a portion of the first upper interconnect layer, and a second capacitor plate having at least a portion of the MIM capacitor layer(s).

Abstract translation: 互补的后端（BEOL）电容器（CBC）结构包括金属氧化物金属（MOM）电容器结构。 MOM电容器结构耦合到集成电路（IC）器件的互连堆叠的第一上互连层。 MOM电容器结构包括互连叠层的至少一个下互连层。 CBC结构还可以包括耦合到MOM电容器结构的互连叠层的第二上互连层。 CBC结构还包括在第一上互连层和第二上互连层之间的至少一个金属绝缘体金属（MIM）电容器层。 此外，CBC结构还可以包括耦合到MOM电容器结构的MIM电容器结构。 MIM电容器结构包括具有第一上部互连层的至少一部分的第一电容器板和具有至少一部分MIM电容器层的第二电容器板。

公开(公告)号：US12224347B2

公开(公告)日：2025-02-11

申请号：US17180219

申请日：2021-02-19

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  Xia Li ,  Haining Yang

IPC: H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/161 ,  H01L29/66

Abstract: An exemplary high performance P-type field-effect transistor (PFET) fabricated on a silicon (Si) germanium (Ge)(SiGe) buffer layer with a SiGe source and drain having a Ge percentage higher than a threshold that causes dislocations at a Si substrate interface is disclosed. A source and drain including a Ge percentage above a 45% threshold provide increased compressive strain in the channel for higher performance of the PFET. Dislocations are avoided in the lattices of the source and drain by forming the PFET on a SiGe buffer layer rather than directly on a Si substrate and the SiGe buffer layer has a percentage of Ge less than a percentage of Ge in the source and drain. In one example, a lattice of the buffer layer is relaxed by implanting dislocations at an interface of the buffer layer and the Si substrate and annealing the buffer layer.

公开(公告)号：US12108610B2

公开(公告)日：2024-10-01

申请号：US17313834

申请日：2021-05-06

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Bin Yang

IPC: H10B61/00 ,  G11C11/16 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

CPC classification number: H10B61/20 ,  G11C11/1655 ,  G11C11/1657 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

Abstract: Disclosed are examples of multiple bit magnetoresistive random access memory (MRAM) cells. A multiple bit MRAM cell may comprise a fixed layer, alternately stacked N tunnel barriers and N free layers, and a tunnel cap. N, which may represent number of bits of the MRAM cell, may be greater than or equal to two. Magnetic moment of the fixed layer may be fixed in one perpendicular direction. Magnetic moments of the free layers may be switchable from one to other perpendicular directions upon application of switch currents. The switch currents may be different for different layers. The magnetic moments of the free layers may be switched separately or otherwise independently of other free layers when the switch currents are applied separately.

公开(公告)号：US11710789B2

公开(公告)日：2023-07-25

申请号：US17369532

申请日：2021-07-07

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Bin Yang ,  Junjing Bao

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/24 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/7831 ,  H01L27/092 ,  H01L29/24 ,  H01L29/517 ,  H01L29/66969

Abstract: Disclosed are semiconductor devices including a double gate metal oxide semiconductor (MOS) transistor and methods for fabricating the same. The double gate MOS transistor includes a first back gate, a second back gate, and a first dielectric layer disposed on the first back gate and on the second back gate. An MX2 material layer is disposed on the first dielectric layer, a second dielectric layer disposed on the MX2 material layer, and a work function metal (WFM) is disposed on the second dielectric layer. A front gate is disposed on the WFM, which fills a space between the first back gate and the second back.

公开(公告)号：US20230061693A1

公开(公告)日：2023-03-02

申请号：US17410690

申请日：2021-08-24

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Junjing Bao ,  Bin Yang

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768

Abstract: Three-dimensional (3D) interconnect structures employing via layer conductive structures in via layers are disclosed. The via layer conductive structures in a signal path in an interconnect structure are disposed in respective via layers adjacent to metal lines in metal layers. The via layer conductive structures increase the conductive cross-sections of signal paths between devices in an integrated circuit (IC) or to/from an external contact. The via layer conductive structures provide one or both of supplementing the height dimensions of metal lines and electrically coupling metal lines in the same or different metal layers to increase the conductive cross-section of a signal path. The increased conductive cross-section reduces current-resistance (IR) drop of signals and increases signal speed. As metal track pitches are reduced in size, signal path resistance increases. The via layer conductive structures are provided to reduce or avoid an even greater increase in resistance in the signal paths.

公开(公告)号：US20210384227A1

公开(公告)日：2021-12-09

申请号：US16895835

申请日：2020-06-08

Applicant: QUALCOMM Incorporated

Inventor： Haining Yang ,  Bin Yang ,  Xia Li

IPC: H01L27/12 ,  H01L29/423 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L29/04 ,  H01L21/84 ,  H01L21/02 ,  H01L21/306 ,  H01L21/762

Abstract: A gate-all-around (GAA) transistor has an insulator on a substrate. The GAA transistor also may have different crystalline structures for P-type work material and N-type work material. The GAA transistor includes one or more channels positioned between a source region and a drain region. The one or more channels, which may be nanowire, nanosheet, or nanoslab semiconductors, are surrounded along a longitudinal axis by gate material. At a first end of the channel is a source region and at an opposite end of the channel is a drain region. To reduce parasitic capacitance between a bottom gate section and a substrate, an insulator is added on the substrate. Further improvements are made in performance of a circuit having both P-type work material and N-type work material by providing different crystalline lattice structures for the work material.