公开(公告)号：US09361228B2

公开(公告)日：2016-06-07

申请号：US14451639

申请日：2014-08-05

Applicant: QUALCOMM Incorporated

Inventor： Andrew Edmund Turner ,  George Patsilaras ,  Bohuslav Rychlik

IPC: G06F12/08

CPC classification number: G06F12/0875 ,  G06F12/0802 ,  G06F12/0886 ,  G06F2212/1021 ,  G06F2212/401 ,  G06F2212/45 ,  G06F2212/608

Abstract: Methods, devices, and non-transitory process-readable storage media for compacting data within cache lines of a cache. An aspect method may include identifying, by a processor of the computing device, a base address (e.g., a physical or virtual cache address) for a first data segment, identifying a data size (e.g., based on a compression ratio) for the first data segment, obtaining a base offset based on the identified data size and the base address of the first data segment, and calculating an offset address by offsetting the base address with the obtained base offset, wherein the calculated offset address is associated with a second data segment. In some aspects, the method may include identifying a parity value for the first data segment based on the base address and obtaining the base offset by performing a lookup on a stored table using the identified data size and identified parity value.

Abstract translation: 用于在高速缓存的高速缓存行中压缩数据的方法，设备和非暂态过程可读存储介质。 方面方法可以包括由计算设备的处理器识别用于第一数据段的基地址（例如，物理或虚拟高速缓存地址），识别第一数据段的数据大小（例如，基于压缩比） 数据段，基于所识别的数据大小和第一数据段的基址获得基本偏移，并且通过利用所获得的基本偏移量偏移基址来计算偏移地址，其中所计算的偏移地址与第二数据相关联 分割。 在一些方面，所述方法可以包括基于所述基地址识别所述第一数据段的奇偶校验值，并通过使用所识别的数据大小和所识别的奇偶校验值对存储的表执行查找来获得所述基本偏移。

公开(公告)号：US20160077973A1

公开(公告)日：2016-03-17

申请号：US14483902

申请日：2014-09-11

Applicant: QUALCOMM Incorporated

Inventor： George PATSILARAS ,  Andrew Edmund Turner ,  Bohuslav Rychlik

IPC: G06F12/08

CPC classification number: G06F12/0893 ,  G06F12/0846 ,  G06F12/0851 ,  G06F12/0886 ,  G06F2212/1044 ,  G06F2212/401

Abstract: Aspects include computing devices, systems, and methods for implementing a cache memory access requests for compressed data using cache bank spreading. In an aspect, cache bank spreading may include determining whether the compressed data of the cache memory access fits on a single cache bank. In response to determining that the compressed data fits on a single cache bank, a cache bank spreading value may be calculated to replace/reinstate bank selection bits of the physical address for a cache memory of the cache memory access request that may be cleared during data compression. A cache bank spreading address in the physical space of the cache memory may include the physical address of the cache memory access request plus the reinstated bank selection bits. The cache bank spreading address may be used to read compressed data from or write compressed data to the cache memory device.

Abstract translation: 方面包括计算设备，系统和方法，用于使用高速缓存存储体扩展来实现用于压缩数据的高速缓存存储器访问请求。 在一方面，高速缓存存储体扩展可以包括确定高速缓冲存储器访问的压缩数据是否适合于单个高速缓存存储体。 响应于确定压缩数据适合于单个高速缓存存储体，可以计算高速缓存存储体扩展值以代替/恢复可以在数据期间清除的高速缓冲存储器访问请求的高速缓冲存储器的物理地址的存储体选择位 压缩。 高速缓冲存储器的物理空间中的高速缓存存储体扩展地址可以包括高速缓冲存储器访问请求的物理地址加上恢复的存储体选择位。 缓存存储体扩展地址可用于从压缩数据读取压缩数据或将压缩数据写入缓存存储器件。

公开(公告)号：US20140189710A1

公开(公告)日：2014-07-03

申请号：US14195976

申请日：2014-03-04

Applicant: QUALCOMM INCORPORATED

Inventor： Sumit SUR ,  James M. Artmeier ,  Mark D. Guzzi ,  Philip T. Mueller ,  Bohuslav Rychlik

IPC: G06F9/50

CPC classification number: G06F9/5094 ,  G06F1/206 ,  G06F1/329 ,  G06F1/3293 ,  G06F11/3058 ,  G06F11/3433 ,  Y02D10/122 ,  Y02D10/16 ,  Y02D10/22 ,  Y02D10/24 ,  Y02D10/34

Abstract: Various embodiments of methods and systems for thermally aware scheduling of workloads in a portable computing device that contains a heterogeneous, multi-processor system on a chip (“SoC”) are disclosed. Because individual processing components in a heterogeneous, multi-processor SoC may exhibit different processing efficiencies at a given temperature, and because more than one of the processing components may be capable of processing a given block of code, thermally aware workload scheduling techniques that compare performance curves of the individual processing components at their measured operating temperatures can be leveraged to optimize quality of service (“QoS”) by allocating workloads in real time, or near real time, to the processing components best positioned to efficiently process the block of code.

Abstract translation: 公开了在包含芯片上的异构多处理器系统（“SoC”）的便携式计算设备中用于热感知调度工作负载的方法和系统的各种实施例。 由于异构多处理器SoC中的单独处理组件可能在给定温度下可能表现出不同的处理效率，并且由于多个处理组件可能能够处理给定的代码块，因此热感知工作负载调度技术可以比较性能 可以利用其测量的工作温度下的各个处理组件的曲线，以便通过实时或接近实时地将工作负载分配给最佳定位以有效地处理代码块的处理组件来优化服务质量（“QoS”）。

公开(公告)号：US20140040552A1

公开(公告)日：2014-02-06

申请号：US13958399

申请日：2013-08-02

Applicant: QUALCOMM Incorporated

Inventor： Bohuslav Rychlik ,  Tzung Ren Tzeng ,  Andrew Evan Gruber ,  Alexei V. Bourd ,  Colin Christopher Sharp ,  Eric Demers

IPC: G06F12/08

CPC classification number: G06F12/0815 ,  G06F12/0811 ,  G06F12/0833 ,  G06F12/0837 ,  G06F12/0891 ,  G06F2212/302

Abstract: A method includes storing, with a first programmable processor, shared variable data to cache lines of a first cache of the first processor. The method further includes executing, with the first programmable processor, a store-with-release operation, executing, with a second programmable processor, a load-with-acquire operation, and loading, with the second programmable processor, the value of the shared variable data from a cache of the second programmable processor.

Abstract translation: 一种方法包括使用第一可编程处理器将共享变量数据存储到第一处理器的第一高速缓存的高速缓存行。 该方法还包括利用第一可编程处理器执行存储释放操作，利用第二可编程处理器执行带有采集操作的负载，并且与第二可编程处理器一起执行共享的值 来自第二可编程处理器的缓存的可变数据。

公开(公告)号：US12093155B2

公开(公告)日：2024-09-17

申请号：US17448864

申请日：2021-09-24

Applicant: QUALCOMM Incorporated

Inventor： Hee Jun Park ,  Bohuslav Rychlik ,  Niraj Shantilal Paliwal

IPC: G06F11/30 ,  G06F7/544 ,  G06F9/50 ,  G06F11/07 ,  G06N3/048

CPC classification number: G06F11/302 ,  G06F7/5443 ,  G06F9/5066 ,  G06F11/0772 ,  G06N3/048

Abstract: Certain aspects of the present disclosure provide techniques for improved hardware utilization. An input data tensor is divided into a first plurality of sub-tensors, and a plurality of logical sub-arrays in a physical multiply-and-accumulate (MAC) array is identified. For each respective sub-tensor of the first plurality of sub-tensors, the respective sub-tensor is mapped to a respective logical sub-array of the plurality of logical sub-arrays, and the respective sub-tensor is processed using the respective logical sub-array.

公开(公告)号：US20240264950A1

公开(公告)日：2024-08-08

申请号：US18163446

申请日：2023-02-02

Applicant: QUALCOMM Incorporated

Inventor： George Patsilaras ,  Engin Ipek ,  Goran Goran ,  Hamza Omar ,  Bohuslav Rychlik ,  Jeffrey Gemar ,  Matthew Severson ,  Andrew Edmund Turner

IPC: G06F12/126 ,  G06F12/0888

CPC classification number: G06F12/126 ,  G06F12/0888 ,  G06F2212/502

Abstract: Providing content-aware cache replacement and insertion policies in processor-based devices is disclosed. In some aspects, a processor-based device comprises a cache memory device and a cache controller circuit of the cache memory device. The cache controller circuit is configured to determine a plurality of content costs for each of a plurality of cached data values in the cache memory device, based on a plurality of bit values of each of the plurality of cached data values. The cache controller circuit is configured to identify, based on the plurality of content costs, a cached data value of the plurality of cached data values associated with a lowest content cost as a target cached data value. The cache controller circuit is also configured to evict the target cached data value from the cache memory device.

公开(公告)号：US20220019534A1

公开(公告)日：2022-01-20

申请号：US16931490

申请日：2020-07-17

Applicant: QUALCOMM Incorporated

Inventor： Andrew Edmund Turner ,  Bohuslav Rychlik ,  George Patsilaras

IPC: G06F12/0815 ,  G06F12/0804 ,  G06F12/10 ,  G06F12/0891

Abstract: Various embodiments include methods and devices for virtual cache coherency. Embodiments may include receiving a snoop for a physical address from a coherent processing device, determining whether an entry for the physical address corresponding to a virtual address in a virtual cache exists in a snoop filter, and sending a cache coherency operation to the virtual cache in response to determining that the entry exists in the snoop filter.

公开(公告)号：US10255181B2

公开(公告)日：2019-04-09

申请号：US15268768

申请日：2016-09-19

Applicant: QUALCOMM Incorporated

Inventor： Andrew Edmund Turner ,  Bohuslav Rychlik

IPC: G06F9/45 ,  G06F12/08 ,  G06F12/0808 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/0877 ,  G06F12/128 ,  G06F12/0804 ,  G06F12/084 ,  G06F9/50 ,  G06F12/12

Abstract: Aspects include computing devices, apparatus, and methods implemented by the apparatus for implementing dynamic input/output (I/O) coherent workload processing on a computing device. Aspect methods may include offloading, by a processing device, a workload to a hardware accelerator for execution using an I/O coherent mode, detecting a dynamic trigger for switching from the I/O coherent mode to a non-I/O coherent mode while the workload is executed by the hardware accelerator, and switching from the I/O coherent mode to a non-I/O coherent mode while the workload is executed by the hardware accelerator.

公开(公告)号：US10114585B2

公开(公告)日：2018-10-30

申请号：US15448203

申请日：2017-03-02

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Hao Chu ,  Subrato Kumar De ,  Dexter Tamio Chun ,  Bohuslav Rychlik ,  Richard Alan Stewart

IPC: G06F3/06 ,  G06F13/16

Abstract: Various aspects are described herein. In some aspects, the present disclosure provides a method of communicating data between an electronic unit of a system-on-chip (SoC) and a dynamic random access memory (DRAM). The method includes initiating a memory transaction corresponding to first data. The method includes determining a non-unique first signature and a unique second signature associated with the first data based on content of the first data. The method includes determining if the non-unique first signature is stored in at least one of a local buffer on the SoC separate from the DRAM or the DRAM. The method includes determining if the unique second signature is stored in at least one of the local buffer or the DRAM based on determining the non-unique first signature is stored. The method includes eliminating the memory transaction with respect to the DRAM based on determining the unique second signature is stored.

公开(公告)号：US09785559B2

公开(公告)日：2017-10-10

申请号：US14725882

申请日：2015-05-29

Applicant: QUALCOMM Incorporated

Inventor： Jason Edward Podaima ,  Bohuslav Rychlik ,  Carlos Javier Moreira ,  Serag Monier GadelRab ,  Paul Christopher John Wiercienski ,  Alexander Miretsky ,  Kyle John Ernewein

IPC: G06F12/12 ,  G06F12/0846 ,  G06F12/1036 ,  G06F12/109

Abstract: Providing memory management unit (MMU) partitioned translation caches, and related apparatuses, methods, and computer-readable media. In this regard, an apparatus comprising an MMU is provided. The MMU comprises a translation cache providing a plurality of translation cache entries defining address translation mappings. The MMU further comprises a partition descriptor table providing a plurality of partition descriptors defining a corresponding plurality of partitions each comprising one or more translation cache entries of the plurality of translation cache entries. The MMU also comprises a partition translation circuit configured to receive a memory access request from a requestor. The partition translation circuit is further configured to determine a translation cache partition identifier (TCPID) of the memory access request, identify one or more partitions of the plurality of partitions based on the TCPID, and perform the memory access request on a translation cache entry of the one or more partitions.