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    Methods and circuits for asymmetric distribution of channel equalization between devices
    53.
    发明授权
    Methods and circuits for asymmetric distribution of channel equalization between devices 有权
    设备之间信道均衡分配不对称的方法和电路

    公开(公告)号：US09077575B2

    公开(公告)日：2015-07-07

    申请号：US13911363

    申请日：2013-06-06

    Applicant: Rambus Inc.

    Inventor： Jared L. Zerbe ,  Fariborz Assaderaghi ,  Brian S. Leibowitz ,  Hae-Chang Lee ,  Jihong Ren ,  Qi Lin

    IPC: H03H7/30 ,  H04L25/03

    CPC classification number: H04L25/03343 ,  H04L25/03057 ,  H04L25/0307 ,  H04L25/03885 ,  H04L2025/03356 ,  H04L2025/03433 ,  H04L2025/03617

    Abstract: A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

    Abstract translation: 收发器架构支持在高性能集成电路（IC）和使用较不复杂的发送器和接收器的一个或多个相对低性能的IC之间延伸的信号通道上的高速通信。 该架构通过在车道的较高性能侧实例化相对复杂的发送和接收均衡电路来补偿通过双向通道通信的IC之间的性能不对称性。 基于在高性能IC的接收机处的信号响应，可以自适应地更新高性能IC中的发送和接收均衡滤波器系数。

    Receiver with enhanced clock and data recovery
    56.
    发明授权
    Receiver with enhanced clock and data recovery 有权

    公开(公告)号：US11277254B2

    公开(公告)日：2022-03-15

    申请号：US17114348

    申请日：2020-12-07

    Applicant: Rambus Inc.

    Inventor： Hae-Chang Lee ,  Brian Leibowitz ,  Jaeha Kim ,  Jafar Savoj

    IPC: H04L7/00 ,  H04L25/06 ,  G06Q10/06 ,  G06Q10/10 ,  H04L7/033 ,  H04L25/03 ,  H04L27/00

    Abstract: A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.

    Phase Control Block for Managing Multiple Clock Domains in Systems with Frequency Offsets
    57.
    发明申请
    Phase Control Block for Managing Multiple Clock Domains in Systems with Frequency Offsets 审中-公开

    公开(公告)号：US20200162233A1

    公开(公告)日：2020-05-21

    申请号：US16659539

    申请日：2019-10-21

    Applicant: Rambus Inc.

    Inventor： Hae-Chang Lee ,  Jared LeVan Zerbe ,  Carl William Werner

    IPC: H04L7/027 ,  H04L7/033 ,  H04L7/00 ,  H03L7/081 ,  H03L7/091

    Abstract: A circuit for performing clock recovery according to a received digital signal. The circuit includes at least an edge sampler and a data sampler for sampling the digital signal, and a clock signal supply circuit. The clock signal supply circuit provides edge clock and data clock signals offset in phase from one another to the respective clock inputs of the edge sampler and the data sampler. A digital phase detector determines if the data clock is early, late or synchronized with respect to data value transitions in the digital signal, and based on that determination provides a phase adjustment signal to the clock signal supply circuit, which is operable to vary phases of the data and edge clock signals accordingly.

    Phase control block for managing multiple clock domains in systems with frequency offsets
    59.
    发明授权
    Phase control block for managing multiple clock domains in systems with frequency offsets 有权

    公开(公告)号：US10454667B2

    公开(公告)日：2019-10-22

    申请号：US15913764

    申请日：2018-03-06

    Applicant: Rambus Inc.

    Inventor： Hae-Chang Lee ,  Jared L. Zerbe ,  Carl William Werner

    IPC: H04L7/02 ,  H04L7/027 ,  H03L7/081 ,  H03L7/091 ,  H04L7/033 ,  H04L7/00

    Abstract: A circuit for performing clock recovery according to a received digital signal. The circuit includes at least an edge sampler and a data sampler for sampling the digital signal, and a clock signal supply circuit. The clock signal supply circuit provides edge clock and data clock signals offset in phase from one another to the respective clock inputs of the edge sampler and the data sampler. A digital phase detector determines if the data clock is early, late or synchronized with respect to data value transitions in the digital signal, and based on that determination provides a phase adjustment signal to the clock signal supply circuit, which is operable to vary phases of the data and edge clock signals accordingly.

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