公开(公告)号：US07138285B2

公开(公告)日：2006-11-21

申请号：US10515198

申请日：2003-05-21

Applicant: Stephen Najda ,  Stewart Duncan McDougall ,  Xuefeng Liu

Inventor： Stephen Najda ,  Stewart Duncan McDougall ,  Xuefeng Liu

IPC: H01L21/00

CPC classification number: B82Y20/00 ,  H01L21/182 ,  H01L33/005 ,  H01S5/3414 ,  H01S5/343 ,  H01S5/34313

Abstract: A method of performing quantum well intermixing in a semiconductor device structure uses a sacrificial part of a cap layer, that is removed after QWI processing, to restore the cap surface to a condition in which high performance contacts are still possible. The method includes: a) forming a layered quantum well structure including a doped cap layer; b) forming an etch stop layer over said cap layer; c) forming a sacrificial layer over said etch stop layer, said etch stop layer having a substantially lower etch rate than said sacrificial layer when exposed to predetermined etch conditions; d) carrying out a quantum well intermixing process on the device structure, which process induces significant damage to at least a portion of the sacrificial layer; e) removing the sacrificial layer in at least a contact region of the device using an etch procedure selective against the etch stop layer to expose said etch stop layer in the contact region; and f) forming a contact over the layered quantum well structure in at least said contact region.

Abstract translation: 在半导体器件结构中进行量子阱混合的方法使用在QWI处理之后去除的覆盖层的牺牲部分，以将盖表面恢复到仍然可能存在高性能接触的状态。 该方法包括：a）形成包括掺杂帽层的层状量子阱结构; b）在所述盖层上形成蚀刻停止层; c）在所述蚀刻停止层上形成牺牲层，当暴露于预定的蚀刻条件时，所述蚀刻停止层具有比所述牺牲层显着更低的蚀刻速率; d）对器件结构进行量子阱混合过程，该过程对牺牲层的至少一部分引起显着的损伤; e）使用对所述蚀刻停止层选择性的蚀刻程序在所述器件的至少接触区域中去除所述牺牲层，以暴露所述接触区域中的所述蚀刻停止层; 以及f）在至少所述接触区域中在层状量子阱结构上形成接触。

公开(公告)号：US20060148106A1

公开(公告)日：2006-07-06

申请号：US10905480

申请日：2005-01-06

Applicant: Hanyi Ding ,  Kai Feng ,  Zhong-Xiang He ,  Xuefeng Liu

Inventor： Hanyi Ding ,  Kai Feng ,  Zhong-Xiang He ,  Xuefeng Liu

IPC: H01L21/00

CPC classification number: H01L23/5227 ,  H01F17/0006 ,  H01F41/046 ,  H01F2019/085 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A mixed-signal chip having a signal transformer located between analog circuitry and digital circuitry. The signal transformer includes a primary winding electrically coupled to the analog circuitry and a secondary winding electrically coupled to the digital circuitry. The primary and secondary windings are magnetically coupled with one another via a magnetic core. The magnetic coupling between the primary and secondary windings inhibits the coupling of electrical noise between the analog and digital circuitries.

Abstract translation: 混合信号芯片，具有位于模拟电路和数字电路之间的信号变压器。 信号变压器包括电耦合到模拟电路的初级绕组和电耦合到数字电路的次级绕组。 初级和次级绕组通过磁芯彼此磁耦合。 初级和次级绕组之间的磁耦合阻碍了模拟和数字电路之间的电气噪声耦合。

公开(公告)号：US09291554B2

公开(公告)日：2016-03-22

申请号：US14170150

申请日：2014-01-31

Applicant: Alexander Kuznetsov ,  Kevin Peterlinz ,  Andrei Shchegrov ,  Leonid Poslavsky ,  Xuefeng Liu

Inventor： Alexander Kuznetsov ,  Kevin Peterlinz ,  Andrei Shchegrov ,  Leonid Poslavsky ,  Xuefeng Liu

IPC: G01N21/84 ,  G01B21/30 ,  G06F17/40 ,  G06F19/00 ,  G01N21/47 ,  G01N21/956 ,  G03F7/20

CPC classification number: G01N21/4788 ,  G01B21/30 ,  G01N21/84 ,  G01N21/95607 ,  G01N2021/95615 ,  G03F7/70625 ,  G06F17/40 ,  G06F19/00

Abstract: Electromagnetic modeling of finite structures and finite illumination for metrology and inspection are described herein. In one embodiment, a method for evaluating a diffracting structure involves providing a model of the diffracting structure. The method involves computing background electric or magnetic fields of an environment of the diffracting structure. The method involves computing scattered electric or magnetic fields from the diffracting structure using a scattered field formulation based on the computed background fields. The method further involves computing spectral information for the model of the diffracting structure based on the computed scattered fields, and comparing the computed spectral information for the model with measured spectral information for the diffracting structure. In response to a good model fit, the method involves determining a physical characteristic of the diffracting structure based on the model of the diffracting structure.

Abstract translation: 本文描述了用于计量和检验的有限结构和有限照明的电磁建模。 在一个实施例中，用于评估衍射结构的方法包括提供衍射结构的模型。 该方法涉及计算衍射结构环境的背景电场或磁场。 该方法涉及使用基于所计算的背景场的散射场拟合来计算衍射结构中的散射电场或磁场。 该方法还涉及基于计算的散射场计算衍射结构模型的光谱信息，并将所计算的模型光谱信息与用于衍射结构的测量光谱信息进行比较。 响应于良好的模型拟合，该方法包括基于衍射结构的模型确定衍射结构的物理特性。

公开(公告)号：US09087925B2

公开(公告)日：2015-07-21

申请号：US13150440

申请日：2011-06-01

Applicant: Xuefeng Liu ,  Robert M. Rassel ,  Steven H. Voldman

Inventor： Xuefeng Liu ,  Robert M. Rassel ,  Steven H. Voldman

IPC: H01L21/84 ,  H01L21/762 ,  H01L27/12 ,  H01L21/8238 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/092

CPC classification number: H01L21/84 ,  H01L21/76243 ,  H01L21/76264 ,  H01L21/823807 ,  H01L21/8249 ,  H01L27/0635 ,  H01L27/0652 ,  H01L27/092 ,  H01L27/1203 ,  H01L27/1207

Abstract: Semiconductor structures and methods of forming semiconductor structures, and more particularly to structures and methods of forming SiGe and/or SiGeC buried layers for SOI/SiGe devices. An integrated structure includes discontinuous, buried layers having alternating Si and SiGe or SiGeC regions. The structure further includes isolation structures at an interface between the Si and SiGe or SiGeC regions to reduce defects between the alternating regions. Devices are associated with the Si and SiGe or SiGeC regions.

Abstract translation: 半导体结构和形成半导体结构的方法，更具体地涉及用于形成用于SOI / SiGe器件的SiGe和/或SiGeC掩埋层的结构和方法。 集成结构包括具有交替的Si和SiGe或SiGeC区域的不连续的掩埋层。 该结构还包括在Si和SiGe或SiGeC区域之间的界面处的隔离结构，以减少交替区域之间的缺陷。 器件与Si和SiGe或SiGeC区域相关联。

公开(公告)号：US09080991B2

公开(公告)日：2015-07-14

申请号：US13073986

申请日：2011-03-28

Applicant: Yung-Ho (Alex) Chuang ,  Vladimir Levinski ,  Xuefeng Liu ,  John Fielden

Inventor： Yung-Ho (Alex) Chuang ,  Vladimir Levinski ,  Xuefeng Liu ,  John Fielden

IPC: G01N21/00 ,  G01N21/95 ,  G01N21/47

CPC classification number: G01N21/9501 ,  G01N2021/479

Abstract: Illumination subsystems of a metrology or inspection system, metrology systems, inspection systems, and methods for illuminating a specimen for metrology measurements or for inspection are provided. One illumination subsystem includes a light source configured to generate coherent pulses of light and a dispersive element positioned in the path of the coherent pulses of light, which is configured to reduce coherence of the pulses of light by mixing spatial and temporal characteristics of light distribution in the pulses of light. The illumination subsystem also includes an electro-optic modulator positioned in the path of the pulses of light exiting the dispersive element and which is configured to reduce the coherence of the pulses of light by temporally modulating the light distribution in the pulses of light. The illumination subsystem is configured to direct the pulses of light from the electro-optic modulator to a specimen.

Abstract translation: 提供了计量或检查系统的照明子系统，计量系统，检查系统和用于计量测量或检查的照明样本的方法。 一个照明子系统包括被配置为产生相干的光脉冲的光源和位于相干脉冲光的路径中的色散元件，该色散元件被配置为通过将光分布的空间和时间特征混合在一起来减小光脉冲的相干性 光的脉冲。 照明子系统还包括位于离开色散元件的光的脉冲的路径中的电光调制器，其被配置为通过暂时调制光脉冲中的光分布来减小光脉冲的相干性。 照明子系统被配置为将来自电光调制器的光脉冲引导到样本。

公开(公告)号：US20140253713A1

公开(公告)日：2014-09-11

申请号：US14351028

申请日：2012-05-14

Applicant: Guangjie Zhai ,  Wenkai Yu ,  Xuefeng Liu ,  Xuri Yao ,  Chao Wang ,  Zhibin Sun

Inventor： Guangjie Zhai ,  Wenkai Yu ,  Xuefeng Liu ,  Xuri Yao ,  Chao Wang ,  Zhibin Sun

IPC: G01N21/25 ,  G01N21/64 ,  G01N21/17

CPC classification number: G01N21/255 ,  G01J1/0414 ,  G01J1/4228 ,  G01N21/17 ,  G01N21/6456 ,  G01S7/4816 ,  G01S7/486 ,  G01S17/89 ,  G02B26/0833 ,  H03K21/38

Abstract: A single-photon or ultra-weak light multi-D imaging spectral system and method. In order to realize rough time resolution, a time-resolved single-photon counting 2D imaging system for forming color or grey imaging is provided. Moreover, in order to realize high-precision time resolution, the system comprises a light source, an imaging spectral measurement unit, an electric detection unit, a system control unit and an algorithm unit. The light carrying information of an object is imaged on a spatial light modulator and randomly modulated according to compressed sensing theory, emergent light of a grating is collected using a point or array single-photon detector, the number of photons and photon arrival time are recorded, and reconstruction is carried out using the compressed sensing algorithm and related algorithm of the spectral imaging. The system provides single-photon detection sensitivity, high time resolution and wide spectral range, and can be applied in numerous new high-tech industries.

Abstract translation: 单光子或超弱光多D成像光谱系统及方法。 为了实现粗糙的时间分辨率，提供了用于形成彩色或灰度成像的时间分辨的单光子计数2D成像系统。 此外，为了实现高精度时间分辨率，该系统包括光源，成像光谱测量单元，电检测单元，系统控制单元和算法单元。 物体的光携带信息在空间光调制器上成像，并且根据压缩感测理论随机调制，使用点或阵列单光子检测器收集光栅的出射光，记录光子数和光子到达时间 ，并利用压缩感知算法和相关的光谱成像算法进行重建。 该系统提供单光子检测灵敏度高，时间分辨率高，光谱范围广，可应用于众多新兴高科技行业。

公开(公告)号：US20140222380A1

公开(公告)日：2014-08-07

申请号：US14170150

申请日：2014-01-31

Applicant: Alexander Kuznetsov ,  Kevin Peterlinz ,  Andrei Shchegrov ,  Leonid Poslavsky ,  Xuefeng Liu

Inventor： Alexander Kuznetsov ,  Kevin Peterlinz ,  Andrei Shchegrov ,  Leonid Poslavsky ,  Xuefeng Liu

IPC: G01N21/27

CPC classification number: G01N21/4788 ,  G01B21/30 ,  G01N21/84 ,  G01N21/95607 ,  G01N2021/95615 ,  G03F7/70625 ,  G06F17/40 ,  G06F19/00

Abstract: Electromagnetic modeling of finite structures and finite illumination for metrology and inspection are described herein. In one embodiment, a method for evaluating a diffracting structure involves providing a model of the diffracting structure. The method involves computing background electric or magnetic fields of an environment of the diffracting structure. The method involves computing scattered electric or magnetic fields from the diffracting structure using a scattered field formulation based on the computed background fields. The method further involves computing spectral information for the model of the diffracting structure based on the computed scattered fields, and comparing the computed spectral information for the model with measured spectral information for the diffracting structure. In response to a good model fit, the method involves determining a physical characteristic of the diffracting structure based on the model of the diffracting structure.

Abstract translation: 本文描述了用于计量和检验的有限结构和有限照明的电磁建模。 在一个实施例中，用于评估衍射结构的方法包括提供衍射结构的模型。 该方法涉及计算衍射结构环境的背景电场或磁场。 该方法涉及使用基于所计算的背景场的散射场拟合来计算衍射结构中的散射电场或磁场。 该方法还涉及基于计算的散射场计算衍射结构模型的光谱信息，并将所计算的模型光谱信息与用于衍射结构的测量光谱信息进行比较。 响应于良好的模型拟合，该方法包括基于衍射结构的模型确定衍射结构的物理特性。

公开(公告)号：US08481380B2

公开(公告)日：2013-07-09

申请号：US12888828

申请日：2010-09-23

Applicant: Xuefeng Liu ,  Richard A. Phelps ,  Robert M. Rassel ,  Xiaowei Tian

Inventor： Xuefeng Liu ,  Richard A. Phelps ,  Robert M. Rassel ,  Xiaowei Tian

IPC: H01L21/337

CPC classification number: H01L29/772 ,  G06F17/50 ,  H01L29/0649 ,  H01L29/0843 ,  H01L29/1066 ,  H01L29/66901 ,  H01L29/808

Abstract: A junction gate field-effect transistor (JFET) for an integrated circuit (IC) chip is provided comprising a source region, a drain region, a lower gate, and a channel, with an insulating shallow trench isolation (STI) region extending from an inner edge of an upper surface of the source region to an inner edge of an upper surface of the drain region, without an intentionally doped region, e.g., an upper gate, coplanar with an upper surface of the IC chip between the source/drain regions. In addition, an asymmetrical quasi-buried upper gate can be included, disposed under a portion of the STI region, but not extending under a portion of the STI region proximate to the drain region. Embodiments of this invention also include providing an implantation layer, under the source region, to reduce Ron. A related method and design structure are also disclosed.

Abstract translation: 提供了一种用于集成电路（IC）芯片的结栅场效应晶体管（JFET），其包括源极区，漏极区，下栅极和沟道，其中绝缘浅沟槽隔离（STI）区域从 源区域的上表面的内边缘到漏极区域的上表面的内边缘，而没有有意掺杂的区域，例如上栅极，与源极/漏极区域之间的IC芯片的上表面共面 。 此外，可以包括设置在STI区域的一部分下方的不对称的准掩埋的上栅极，但不在靠近漏极区域的STI区域的一部分下方延伸。 本发明的实施例还包括在源极区域下提供注入层以减少Ron。 还公开了相关的方法和设计结构。

公开(公告)号：US08338265B2

公开(公告)日：2012-12-25

申请号：US12269069

申请日：2008-11-12

Applicant: Douglas D. Coolbaugh ,  Jeffrey B. Johnson ,  Peter J. Lindgren ,  Xuefeng Liu ,  James S. Nakos ,  Bradley A. Orner ,  Robert M. Rassel ,  David C. Sheridan

Inventor： Douglas D. Coolbaugh ,  Jeffrey B. Johnson ,  Peter J. Lindgren ,  Xuefeng Liu ,  James S. Nakos ,  Bradley A. Orner ,  Robert M. Rassel ,  David C. Sheridan

IPC: H01L21/76

CPC classification number: H01L21/743 ,  H01L21/28518 ,  H01L21/76224 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/41 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A trench contact silicide is formed on an inner wall of a contact trench that reaches to a buried conductive layer in a semiconductor substrate to reduce parasitic resistance of a reachthrough structure. The trench contact silicide is formed at the bottom, on the sidewalls of the trench, and on a portion of the top surface of the semiconductor substrate. The trench is subsequently filled with a middle-of-line (MOL) dielectric. A contact via may be formed on the trench contact silicide. The trench contact silicide may be formed through a single silicidation reaction with a metal layer or through multiple silicidation reactions with multiple metal layers.

Abstract translation: 沟槽接触硅化物形成在接触沟槽的内壁上，该接触沟槽的内壁到达半导体衬底中的掩埋导电层，以减小通孔结构的寄生电阻。 沟槽接触硅化物形成在底部，沟槽的侧壁上以及在半导体衬底的顶表面的一部分上。 沟槽随后填充有中间线（MOL）电介质。 可以在沟槽接触硅化物上形成接触通孔。 沟槽接触硅化物可以通过与金属层的单一硅化反应或通过与多个金属层的多次硅化反应形成。

公开(公告)号：US20120132992A1

公开(公告)日：2012-05-31

申请号：US13367646

申请日：2012-02-07

Applicant: Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Zhenrong Jin ,  Xuefeng Liu ,  Yun Shi

Inventor： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Zhenrong Jin ,  Xuefeng Liu ,  Yun Shi

IPC: H01L27/12

CPC classification number: H01L27/088 ,  H01L21/823462 ,  H01L21/823481 ,  H01L27/1207

Abstract: A first field effect transistor includes a gate dielectric and a gate electrode located over a first portion of a top semiconductor layer in a semiconductor-on-insulator (SOI) substrate. A second field effect transistor includes a portion of a buried insulator layer and a source region and a drain region located underneath the buried insulator layer. In one embodiment, the gate electrode of the second field effect transistor is a remaining portion of the top semiconductor layer. In another embodiment, the gate electrode of the second field effect transistor is formed concurrently with the gate electrode of the first field effect transistor by deposition and patterning of a gate electrode layer. The first field effect transistor may be a high performance device and the second field effect transistor may be a high voltage device. A design structure for the semiconductor structure is also provided.

Abstract translation: 第一场效应晶体管包括栅极电介质和位于绝缘体上半导体（SOI））衬底中顶部半导体层的第一部分上方的栅电极。 第二场效应晶体管包括掩埋绝缘体层的一部分和位于掩埋绝缘体层下方的源区和漏区。 在一个实施例中，第二场效应晶体管的栅电极是顶部半导体层的剩余部分。 在另一个实施例中，第二场效应晶体管的栅极通过栅极电极层的沉积和图案化与第一场效应晶体管的栅电极同时形成。 第一场效应晶体管可以是高性能器件，第二场效应晶体管可以是高电压器件。 还提供了用于半导体结构的设计结构。