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    Vertical semiconductor devices
    52.
    发明授权
    Vertical semiconductor devices 有权

    公开(公告)号：US11925020B2

    公开(公告)日：2024-03-05

    申请号：US17473006

    申请日：2021-09-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Shinhwan Kang ,  Younghwan Son ,  Haemin Lee ,  Kohji Kanamori ,  Jeehoon Han

    IPC: H10B43/00 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

    CPC classification number: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/35

    Abstract: A vertical semiconductor device may include a stacked structure and a plurality of channel structures. The stacked structure may include insulation layers and gate patterns alternately and repeatedly stacked on a substrate. The stacked structure may extend in a first direction parallel to an upper surface of the substrate. The gate patterns may include at least ones of first gate patterns. The stacked structure may include a sacrificial pattern between the first gate patterns. The channel structures may pass through the stacked structure. Each of the channel structures may extend to the upper surface of the substrate, and each of the channel structures may include a charge storage structure and a channel. Ones of the channel structures may pass through the sacrificial pattern in the stacked structure to the upper surface of the substrate, and may extend to the upper surface of the substrate.

    SEMICONDUCTOR DEVICE
    54.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20230262972A1

    公开(公告)日：2023-08-17

    申请号：US18190253

    申请日：2023-03-27

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sangyoun JO ,  Kohji Kanamori ,  Kwangyoung Jung ,  Jeehoon Han

    IPC: H10B41/27 ,  H01L23/528 ,  H01L23/522 ,  H10B41/10 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40

    CPC classification number: H10B41/27 ,  H01L23/528 ,  H01L23/5226 ,  H10B41/10 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40

    Abstract: A semiconductor device includes a substrate including a first plate portion and a second plate portion, a stack structure including interlayer insulating layers and gate electrodes alternately stacked on the substrate, a first block separation structure on the first plate portion and a second block separation structure on the first plate portion. Each of the first and second block separation structures includes first separation regions, a cell array separation structure including a second separation region connected to the first separation regions and channel structures penetrating the stack structure, wherein the stack structure includes first stack structures separated by the first separation regions of the first block separation structure and extending in the first direction, second stack structures separated by the first separation regions of the second block separation structure, and at least one third stack structure separated from the first and second stack structures by the cell array separation structure.

    Semiconductor device with reduced vertical height
    55.
    发明授权
    Semiconductor device with reduced vertical height 有权

    公开(公告)号：US11563023B2

    公开(公告)日：2023-01-24

    申请号：US16792256

    申请日：2020-02-16

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jongseon Ahn ,  Youngjin Kwon ,  Jeehoon Han

    IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L29/423

    Abstract: A semiconductor device includes a channel structure arranged on a substrate and extending in a first direction perpendicular to a top surface of the substrate, the channel structure including a channel layer and a gate insulating layer; a plurality of insulating layers arranged on the substrate and surrounding the channel structure, the plurality of insulating layers spaced apart from each other in the first direction; a plurality of first gate electrodes surrounding the channel structure; and a plurality of second gate electrodes surrounding the channel structure. Between adjacent insulating layers from among the plurality of insulating layers are arranged a first gate electrode from among the plurality of first gate electrodes spaced apart along the first direction from a second gate electrode from among the plurality of second gate electrodes.

    Vertical-type nonvolatile memory device including an extension area contact structure
    56.
    发明授权
    Vertical-type nonvolatile memory device including an extension area contact structure 有权

    公开(公告)号：US11552099B2

    公开(公告)日：2023-01-10

    申请号：US16928306

    申请日：2020-07-14

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kyungdong Kim ,  Younghwan Son ,  Jeehoon Han

    IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11556

    Abstract: A vertical-type nonvolatile memory device including: a substrate including a cell array area and an extension area, the extension area extending in a first direction from the cell array area and including contacts; a channel structure extending in a vertical direction from the substrate; a first stack structure including gate electrode layers and interlayer insulating layers alternately stacked along sidewalls of the channel structure; a plurality of division areas extending in the first direction and dividing the cell array area and the extension area in a second direction perpendicular to the first direction; in the extension area, two insulating layer dams are arranged between two division areas adjacent to each other; a second stack structure including sacrificial layers and interlayer insulating layers alternately stacked on the substrate between the two insulating layer dams; and an electrode pad connected to a first gate electrode layer in the extension area.

    Semiconductor devices
    57.
    发明授权
    Semiconductor devices 有权

    公开(公告)号：US11515322B2

    公开(公告)日：2022-11-29

    申请号：US16890500

    申请日：2020-06-02

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seogoo Kang ,  Daehyun Jang ,  Jaeryong Sim ,  Jongseon Ahn ,  Jeehoon Han

    IPC: H01L27/11582 ,  H01L27/11575 ,  H01L27/11548 ,  H01L27/11556

    Abstract: A semiconductor device includes a peripheral circuit region including a first substrate and circuit elements on the first substrate; and a memory cell region including a second substrate on an upper portion of the first substrate, gate electrodes spaced apart from each other and vertically stacked on the second substrate, channel structures extending vertically through the gate electrodes to the second substrate, first separation regions penetrating through the gate electrodes between the channel structures and extending in one direction, and a second separation region extending vertically to penetrate through the second substrate from above and having a bent portion due to a change in width.

    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES
    59.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES 有权

    公开(公告)号：US20210384220A1

    公开(公告)日：2021-12-09

    申请号：US17406245

    申请日：2021-08-19

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： JONGSEON AHN ,  Jaeryong Sim ,  Giyong Chung ,  Jeehoon Han

    IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L23/60 ,  H01L27/11573 ,  H01L29/06 ,  H01L21/311 ,  H01L27/1157

    Abstract: A three-dimensional (3D) semiconductor memory device including; first and second semiconductor layers horizontally spaced apart from each other; a buried insulating layer between the first and second semiconductor layers; a first cell array structure disposed on the first semiconductor layer, and a second cell array structure disposed on the second semiconductor layer; and an isolation structure disposed on the buried insulating layer between the first and second cell array structures, wherein the first cell array structure includes: an electrode structure including electrodes, which are stacked in a direction perpendicular to a top surface of the first semiconductor layer; and a first source structure disposed between the first semiconductor layer and the electrode structure, the first source structure is extended onto the buried insulating layer, and the isolation structure is between the first source structure of the first cell array structure and a second source structure of the second cell array structure.

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