公开(公告)号：US20240237346A1

公开(公告)日：2024-07-11

申请号：US18355888

申请日：2023-07-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul SHARANGPANI ,  Raghuveer S. MAKALA ,  Adarsh RAJASHEKHAR ,  Fei ZHOU ,  Bing ZHOU ,  Senaka KANAKAMEDALA ,  Roshan Jayakhar TIRUKKONDA ,  Kartik SONDHI

IPC: H10B43/27 ,  H01L23/522 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

CPC classification number: H10B43/27 ,  H01L23/5226 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

Abstract: A method of forming a memory device includes forming an alternating stack of insulating layers including a first insulating material and sacrificial material layers including a first sacrificial material over a substrate, forming a memory opening through the alternating stack, performing a first selective material deposition process that selectively grows a second sacrificial material from physically exposed surfaces of the sacrificial material layers to form a vertical stack of sacrificial material portions; forming a memory opening fill structure in the memory opening, where the memory opening fill structure includes a vertical stack of memory elements and a vertical semiconductor channel, and replacing a combination of the vertical stack of sacrificial material portions and the sacrificial material layers with electrically conductive layers.

公开(公告)号：US20240237343A9

公开(公告)日：2024-07-11

申请号：US18350552

申请日：2023-07-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Bing ZHOU ,  Monica TITUS ,  Raghuveer S. MAKALA ,  Rahul SHARANGPANI ,  Senaka KANAKAMEDALA

IPC: H10B43/27 ,  H10B41/27

CPC classification number: H10B43/27 ,  H10B41/27

Abstract: A etch stop structure is formed a sacrificial memory opening fill structure formed within a first-tier memory opening vertically extending through a first-tier alternating stack of first insulating layers and first spacer material layers. The etch stop structure may include a conductive etch stop plate that is formed over a sacrificial memory opening fill material portion inside the first-tier memory opening, or may include a semiconductor plug which is selectively grown from sidewalls of an etch stop semiconductor material layer that is formed over the first-tier alternating stack. A second-tier alternating stack of second insulating layers and second spacer material layers is formed over the first-tier alternating stack and the etch stop structure.

公开(公告)号：US20240179897A1

公开(公告)日：2024-05-30

申请号：US18351205

申请日：2023-07-12

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul SHARANGPANI ,  Raghuveer S. MAKALA ,  Adarsh RAJASHEKHAR ,  Fei ZHOU

IPC: H10B41/27 ,  G11C16/04 ,  H01L23/522 ,  H01L23/528 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B41/27 ,  G11C16/0483 ,  H01L23/5226 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and containing a vertical semiconductor channel and a memory film. The memory film includes a tunneling dielectric layer, a continuous charge storage material layer vertically extending through a plurality of the electrically conductive layers, a vertical stack of discrete charge storage elements located at levels of the electrically conductive layers and contacting a respective surface segment of an outer sidewall of the continuous charge storage material layer, and a vertical stack of discrete blocking dielectric material portions containing silicon atoms and oxygen atoms and located at the levels of the electrically conductive layers and vertically spaced apart from each other.

公开(公告)号：US20240138149A1

公开(公告)日：2024-04-25

申请号：US18350552

申请日：2023-07-10

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Bing ZHOU ,  Monica TITUS ,  Raghuveer S. MAKALA ,  Rahul SHARANGPANI ,  Senaka KANAKAMEDALA

IPC: H10B43/27 ,  H10B41/27

CPC classification number: H10B43/27 ,  H10B41/27

Abstract: A etch stop structure is formed a sacrificial memory opening fill structure formed within a first-tier memory opening vertically extending through a first-tier alternating stack of first insulating layers and first spacer material layers. The etch stop structure may include a conductive etch stop plate that is formed over a sacrificial memory opening fill material portion inside the first-tier memory opening, or may include a semiconductor plug which is selectively grown from sidewalls of an etch stop semiconductor material layer that is formed over the first-tier alternating stack. A second-tier alternating stack of second insulating layers and second spacer material layers is formed over the first-tier alternating stack and the etch stop structure.

公开(公告)号：US20230354609A1

公开(公告)日：2023-11-02

申请号：US18346504

申请日：2023-07-03

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul SHARANGPANI ,  Senaka KANAKAMEDALA ,  Raghuveer S. MAKALA ,  Roshan Jayakhar TIRUKKONDA ,  Kartik SONDHI

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

Abstract: A method of forming a structure includes forming an alternating stack of first material layers and second material layers over a substrate; forming an etch mask material layer containing an opening over the alternating stack; performing a first anisotropic etch process that etches unmasked upper portions of the alternating stack to form a via opening below the opening in the etch mask material layer; forming a combination of a non-conformal cladding liner and a conformal sacrificial spacer layer over the etch mask material layer and in peripheral portions of the via opening; performing a punch-through process that etches a horizontally-extending portion of the conformal sacrificial spacer layer from a bottom portion of the via opening; and vertically extending the via opening by performing a second anisotropic etch process that etches unmasked lower portions of the alternating stack selective to the non-conformal cladding liner and the conformal sacrificial spacer layer.

公开(公告)号：US20230301077A1

公开(公告)日：2023-09-21

申请号：US17655272

申请日：2022-03-17

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Adarsh RAJASHEKHAR ,  Raghuveer S. MAKALA ,  Masanori TSUTSUMI ,  Fei ZHOU

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  G11C16/04

CPC classification number: H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  G11C16/0483

Abstract: A semiconductor structure includes a doped single crystalline semiconductor material layer, a metal or metal alloy source contact layer located over a back side of the doped single crystalline semiconductor material layer, a dielectric isolation layer located over a front side of the doped single crystalline semiconductor material layer, an alternating stack of insulating layers and electrically conductive layers located over the dielectric isolation layer, a memory opening vertically extending through the alternating stack and the dielectric isolation layer and at least partially through the doped single crystalline semiconductor material layer, a memory film and a vertical semiconductor channel located within the memory opening, such that the vertical semiconductor channel vertically extends through the dielectric isolation layer and into the doped single crystalline semiconductor material layer, and a single crystalline semiconductor pedestal contacting the doped single crystalline semiconductor material layer and the vertical semiconductor channel.

公开(公告)号：US20230223267A1

公开(公告)日：2023-07-13

申请号：US17573466

申请日：2022-01-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul SHARANGPANI ,  Fei ZHOU ,  Raghuveer S. MAKALA ,  Yujin TERASAWA ,  Naoki TAKEGUCHI ,  Kensuke YAMAGUCHI

IPC: H01L21/285 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11597 ,  H01L27/24 ,  H01L21/768 ,  C23C16/14 ,  C23C16/455

CPC classification number: H01L21/28568 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11597 ,  H01L27/2481 ,  H01L21/76876 ,  C23C16/14 ,  C23C16/45525 ,  H01L21/76846

Abstract: A method of depositing a metal includes providing a structure a process chamber, and providing a metal fluoride gas and a growth-suppressant gas into the process chamber to deposit the metal over the structure. The metal may comprise a word line or another conductor of a three-dimensional memory device.

公开(公告)号：US20230128682A1

公开(公告)日：2023-04-27

申请号：US18145275

申请日：2022-12-22

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kartik SONDHI ,  Raghuveer S. MAKALA ,  Adarsh RAJASHEKHAR ,  Rahul SHARANGPANI ,  Fei ZHOU

IPC: H10B41/27 ,  G11C16/04 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical semiconductor channel and a memory film. The memory film includes a memory material layer having a straight inner cylindrical sidewall that vertically extends through a plurality of electrically conductive layers within the alternating stack without lateral undulation and a laterally-undulating outer sidewall having outward lateral protrusions at levels of the plurality of electrically conductive layers.

公开(公告)号：US20220352198A1

公开(公告)日：2022-11-03

申请号：US17244456

申请日：2021-04-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul SHARANGPANI ,  Raghuveer S. MAKALA

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11565

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, and memory opening fill structures located in the memory openings. Each of the memory opening fill structures includes a vertical stack of memory elements located at levels of the electrically conductive layers. Each of the electrically conductive layers includes a metallic barrier liner containing an intermetallic compound of at least two elements that includes a first metal element including Ta or Ti, and a second metal element including at least one of Al or Mo, and metallic barrier liner containing less than 10 atomic percent of nitrogen and oxygen, and a metallic fill material layer contacting the metallic barrier liner.

公开(公告)号：US20220189993A1

公开(公告)日：2022-06-16

申请号：US17122360

申请日：2020-12-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Roshan TIRUKKONDA ,  Ramy Nashed Bassely SAID ,  Senaka KANAKAMEDALA ,  Rahul SHARANGPANI ,  Raghuveer S. MAKALA ,  Adarsh RAJASHEKHAR ,  Fei ZHOU

IPC: H01L27/11597 ,  H01L27/11587 ,  H01L27/1159

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers and memory stack structures vertically extending through the alternating stack. Each of the memory stack structures includes a vertical semiconductor channel and a vertical stack of ferroelectric memory elements surrounding the vertical semiconductor channel and located at levels of the electrically conductive layers. Each of the ferroelectric memory elements includes a respective vertical stack of a first ferroelectric material portion and a second ferroelectric material portion that differs from the first ferroelectric material portion by at least one of a material composition and a lateral thickness.