公开(公告)号：US11189351B2

公开(公告)日：2021-11-30

申请号：US16832293

申请日：2020-03-27

Applicant: SanDisk Technologies LLC

Inventor： Yu-Chung Lien ,  Sarath Puthenthermadam ,  Huai-Yuan Tseng

IPC: G11C11/34 ,  G11C16/26 ,  G11C16/04 ,  H01L27/11582

Abstract: A memory apparatus and method of operation is provided. The apparatus includes a block of memory cells arranged in strings and connected to word lines overlying one another in a stack. The block is divided into first and second sub-blocks programmed as a whole in a sub-block mode and includes a particular group connected to a particular word line. A control circuit determines whether the particular group being read is in the second sub-block when operating in the sub-block mode. The control circuit also determines whether one of the first and second sub-blocks is not programmed based on whether the particular group being read is in the second sub-block. The control circuit applies an adjusted read voltage to the word lines of the one of the first and second sub-blocks while reading the particular group based on whether the one of the first and second sub-blocks is not programmed.

公开(公告)号：US20210304822A1

公开(公告)日：2021-09-30

申请号：US16832293

申请日：2020-03-27

Applicant: SanDisk Technologies LLC

Inventor： Yu-Chung Lien ,  Sarath Puthenthermadam ,  Huai-Yuan Tseng

IPC: G11C16/26 ,  G11C16/04

Abstract: A memory apparatus and method of operation is provided. The apparatus includes a block of memory cells arranged in strings and connected to word lines overlying one another in a stack. The block is divided into first and second sub-blocks programmed as a whole in a sub-block mode and includes a particular group connected to a particular word line. A control circuit determines whether the particular group being read is in the second sub-block when operating in the sub-block mode. The control circuit also determines whether one of the first and second sub-blocks is not programmed based on whether the particular group being read is in the second sub-block. The control circuit applies an adjusted read voltage to the word lines of the one of the first and second sub-blocks while reading the particular group based on whether the one of the first and second sub-blocks is not programmed.

公开(公告)号：US20210027850A1

公开(公告)日：2021-01-28

申请号：US17066663

申请日：2020-10-09

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Yu-Chung Lien

IPC: G11C16/34 ,  G11C16/24 ,  G11C16/08 ,  G11C16/04 ,  G11C16/26

Abstract: A methodology and structure for performing an erase verify in non-volatile memory is described. Both the odd wordlines and the even wordlines are driven to a high voltage level. This can be done simultaneously. The simultaneous charging of both the odd wordlines and the even wordlines, even when the erase verify will occur on only one of the odd or even wordlines reduces RC delay in the charging of the wordlines. After the odd and even wordlines are charged, then one set of wordlines, either the odd or even wordlines, is dropped to the erase verify voltage. The erase sense operation is then performed.

公开(公告)号：US20190378583A1

公开(公告)日：2019-12-12

申请号：US16205165

申请日：2018-11-29

Applicant: SanDisk Technologies LLC

Inventor： Yu-Chung Lien ,  Xiang Yang ,  Zhenming Zhou ,  Deepanshu Dutta ,  Huai-Yuan Tseng

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/32

Abstract: An apparatus, system, and method are disclosed for identifying and selecting a subgroup of memory cells for use during a programming or erasing operation, in order to execute the programming or erasing operation in less time, while avoiding over and under programming errors. Memory devices disclosed herein may include a state change/programming circuit, a counting circuit, a determination circuit, an identification circuit, and/or a subgroup selection circuit, where each of these circuits are configured to perform operations related to the overall process of identifying and selecting the subgroup of memory cells for utilization during a programming operation.

公开(公告)号：US11972809B2

公开(公告)日：2024-04-30

申请号：US17682280

申请日：2022-02-28

Applicant: SanDisk Technologies LLC

Inventor： Sujjatul Islam ,  Yu-Chung Lien ,  Ravi Kumar ,  Xue Pitner

IPC: G11C16/04 ,  G11C16/14 ,  G11C16/24 ,  G11C16/34 ,  G11C16/26 ,  H10B41/27 ,  H10B43/27

CPC classification number: G11C16/3427 ,  G11C16/0483 ,  G11C16/14 ,  G11C16/24 ,  G11C16/26 ,  H10B41/27 ,  H10B43/27

Abstract: A non-volatile semiconductor memory device includes non-volatile storage elements and one or more control circuits in communication with the non-volatile storage elements. The one or more control circuits are configured to determine for a program iteration of a program operation on a word line whether a condition is met and in response to determining that the condition is met, identify one or more memory cells of the word line that are in an erased state that have a threshold voltage higher than an erase threshold voltage and perform the program iteration of the program operation. The program iteration includes applying a first bitline inhibit voltage to bitlines connected to the identified one or more memory cells and a second bitline inhibit voltage to bitlines connected to one or more memory cells that are in the erased state that do not have a threshold voltage higher than the erase threshold voltage.

公开(公告)号：US11972803B2

公开(公告)日：2024-04-30

申请号：US17571124

申请日：2022-01-07

Applicant: SanDisk Technologies LLC

Inventor： Yu-Chung Lien ,  Fanqi Wu ,  Jiahui Yuan

IPC: G11C11/34 ,  G11C7/10 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30

CPC classification number: G11C16/102 ,  G11C7/1048 ,  G11C16/08 ,  G11C16/26 ,  G11C16/30

Abstract: A memory device that uses different programming parameters base on the word line(s) to be programmed is described. The programming parameter PROGSRC_PCH provides a pre-charge voltage to physical word lines. In some instances, the PROGSRC_PCH voltage is decoupled, and a new PROGSRC_PCH represents an adjusted (e.g., increased) pre-charge voltage for a certain physical word line or word line zone (i.e., predetermined group of word lines). Using different PROGSRC_PCH voltages can limit or prevent Vt distribution window degradation, particularly for relatively low physical word lines. Additionally, the overall programming time and average current consumed can also be reduced.

公开(公告)号：US20230307071A1

公开(公告)日：2023-09-28

申请号：US17701320

申请日：2022-03-22

Applicant: SanDisk Technologies LLC

Inventor： Xue Bai Pitner ,  Yu-Chung Lien ,  Ravi Kumar ,  Jiahui Yuan ,  Bo Lei ,  Zhenni Wan

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26

CPC classification number: G11C16/3459 ,  G11C16/3404 ,  G11C16/102 ,  G11C16/26

Abstract: The memory device includes a plurality of memory cells, which include a first set of memory cells and a second set of memory cells. A controller is in communication with the memory cells. The controller is configured to, in a first programming pass and then a second programming pass, program the memory cells of the first and second sets to respective final threshold voltages associated with a plurality of programmed data states. The controller is further configured to, in the first programming pass, verify the first set of memory cells at a first set of checkpoint data states and verify the second set of memory cells at a second set of checkpoint data states that is different than the first set of checkpoint data states.

公开(公告)号：US11758718B2

公开(公告)日：2023-09-12

申请号：US17375476

申请日：2021-07-14

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yu-Chung Lien ,  Abhijith Prakash ,  Keyur Payak ,  Jiahui Yuan ,  Huai-Yuan Tseng ,  Shinsuke Yada ,  Kazuki Isozumi

IPC: G11C7/00 ,  H10B41/27 ,  H01L29/78 ,  G11C5/02 ,  H10B43/27

CPC classification number: H10B41/27 ,  G11C5/025 ,  H01L29/7827 ,  H10B43/27

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, first memory opening fill structures extending through the alternating stack and including a respective first vertical semiconductor channel having a tubular section and a semi-tubular section, second memory opening fill structures, first bit lines electrically connected to a respective subset of the first drain regions, second bit lines electrically connected to a respective subset of the second drain regions, and an erase voltage application circuit configured to electrically bias the first bit lines at a first bit line erase voltage and the second bit lines at a second bit line erase voltage during an erase operation. The first bit line erase voltage is greater than the second bit line erase voltage.

公开(公告)号：US20230253049A1

公开(公告)日：2023-08-10

申请号：US17666810

申请日：2022-02-08

Applicant: SanDisk Technologies LLC

Inventor： Yu-Chung Lien ,  Deepanshu Dutta ,  Sarath Puthenthermadam ,  Jiahui Yuan

IPC: G11C16/10 ,  G11C16/26 ,  G11C16/08 ,  G11C16/24 ,  G11C16/30

CPC classification number: G11C16/102 ,  G11C16/26 ,  G11C16/08 ,  G11C16/24 ,  G11C16/30

Abstract: A non-volatile semiconductor memory device, described herein, comprises a bit line, a source line, a memory string comprising a plurality of memory cells connected in series between the source line and the bit line, and control circuitry coupled to the plurality of memory cells, the source line, and the bit line. The control circuitry is configured to: determine if a program operation is a single-bit program operation or multi-bit program operation; in response to the determination, identify a voltage level to set the source line to during performance of the program operation; and perform the program operation on the memory string, the program operation including setting the source line to the voltage level.

公开(公告)号：US11664075B2

公开(公告)日：2023-05-30

申请号：US17461922

申请日：2021-08-30

Applicant: SanDisk Technologies LLC

Inventor： Yu-Chung Lien ,  Jiahui Yuan ,  Tomer Eliash

IPC: G11C16/10 ,  G11C16/16 ,  G11C16/04 ,  G11C16/08 ,  G11C16/26

CPC classification number: G11C16/102 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/16 ,  G11C16/26

Abstract: Apparatuses and techniques are described for programming a multi-tier block in which sub-blocks are arranged in respective tiers. When a program operation involves the source-side sub-block, the NAND strings are pre-charged from the source line. When a program operation involves the drain-side sub-block, the NAND strings are pre-charged from the bit line. When a program operation involves an interior sub-block, the NAND strings can be pre-charged from the bit line if all sub-blocks on the drain side of the interior sub-block are erased, or from the source line if all sub-blocks on the source side of the interior sub-block are erased. A table can be provided which identifies free blocks, free sub-blocks and a corresponding program order. If such a table is not available, the sub-blocks can be read to determine whether they are programmed.