公开(公告)号：US20160035872A1

公开(公告)日：2016-02-04

申请号：US14449192

申请日：2014-08-01

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： Nicolas Loubet ,  Hong He ,  James Kuss

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/12

CPC classification number: H01L29/785 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/66795

Abstract: A substrate layer formed of a first semiconductor material includes adjacent first and second regions. Fin structures are formed from the substrate layer in both the first and second regions. At least the side walls of the fin structures in the second region are covered with an epitaxially grown layer of second semiconductor material. A drive in process is performed to convert the fin structures in the second region from the first semiconductor material to the second semiconductor material. The first semiconductor material is, for example, silicon, and the second semiconductor material is, for example, silicon germanium or silicon carbide. The fin structures in the first region are provided for a FinFET of a first (for example, n-channel) conductivity type while the fin structures in the second region are provided for a FinFET of a second (for example, p-channel) conductivity type.

Abstract translation: 由第一半导体材料形成的衬底层包括相邻的第一和第二区域。 翅片结构由第一和第二区域中的基底层形成。 至少第二区域中的翅片结构的侧壁被外延生长的第二半导体材料层覆盖。 执行处理中的驱动以将第二区域中的鳍状结构从第一半导体材料转换成第二半导体材料。 第一半导体材料是例如硅，第二半导体材料是例如硅锗或碳化硅。 第一区域中的鳍结构被提供用于第一（例如，n沟道）导电类型的FinFET，而第二区域中的翅片结构被设置用于具有第二（例如，p沟道）导电性的FinFET 类型。

公开(公告)号：US20160013096A1

公开(公告)日：2016-01-14

申请号：US14856949

申请日：2015-09-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMicroelectronics, Inc. ,  COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Bruce B. Doris ,  Shom Ponoth ,  Prasanna Khare ,  Qing Liu ,  Nicolas Loubet ,  Maud Vinet

IPC: H01L21/762 ,  H01L21/768 ,  H01L29/06 ,  H01L29/417 ,  H01L29/08 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L21/76879 ,  H01L21/0217 ,  H01L21/76224 ,  H01L21/76283 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76897 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66568 ,  H01L29/66628 ,  H01L29/78609

Abstract: A shallow trench is formed to extend into a handle substrate of a semiconductor-on-insulator (SOI) layer. A dielectric liner stack of a dielectric metal oxide layer and a silicon nitride layer is formed in the shallow trench, followed by deposition of a shallow trench isolation fill portion. The dielectric liner stack is removed from above a top surface of a top semiconductor portion, followed by removal of a silicon nitride pad layer and an upper vertical portion of the dielectric metal oxide layer. A divot laterally surrounding a stack of a top semiconductor portion and a buried insulator portion is filled with a silicon nitride portion. Gate structures and source/drain structures are subsequently formed. The silicon nitride portion or the dielectric metal oxide layer functions as a stopping layer during formation of source/drain contact via holes, thereby preventing electrical shorts between source/drain contact via structures and the handle substrate.

公开(公告)号：US09219133B2

公开(公告)日：2015-12-22

申请号：US13905586

申请日：2013-05-30

Applicant: STMICROELECTRONICS, INC.

Inventor： Nicolas Loubet ,  Pierre Morin

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/06

CPC classification number: H01L29/7848 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/66439 ,  H01L29/66795

Abstract: A method of making a semiconductor device includes forming a first spacer for at least one gate stack on a first semiconductor material layer, and forming a respective second spacer for each of source and drain regions adjacent the at least one gate. Each second spacer has a pair of opposing sidewalls and an end wall coupled thereto. The method includes filling the source and drain regions with a second semiconductor material while the first and second spacers provide confinement.

Abstract translation: 制造半导体器件的方法包括在第一半导体材料层上形成用于至少一个栅极叠层的第一间隔物，以及与邻近所述至少一个栅极的每个源区和漏区形成相应的第二间隔物。 每个第二间隔件具有一对相对的侧壁和与其连接的端壁。 该方法包括用第二半导体材料填充源区和漏区，而第一和第二间隔件提供约束。

公开(公告)号：US20150325487A1

公开(公告)日：2015-11-12

申请号：US14802407

申请日：2015-07-17

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： Nicolas Loubet ,  Prasanna Khare ,  Qing Liu ,  Balasubramanian Pranatharthiharan ,  Shom Ponoth

IPC: H01L21/84 ,  H01L21/02 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/762

CPC classification number: H01L21/845 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/76224 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/1211 ,  H01L29/6653 ,  H01L29/6656

Abstract: On a first semiconductor material substrate, an overlying sacrificial layer formed of a second semiconductor material is deposited. In a first region, a first semiconductor material region is formed over the sacrificial layer. In a second region, a second semiconductor material region is formed over the sacrificial layer. The first semiconductor material region is patterned to define a first FinFET fin. The second semiconductor material region is patterned to define a second FinFET fin. The fins are each covered with a cap and sidewall spacer. The sacrificial layer formed of the second semiconductor material is then selectively removed to form an opening below each of the first and second FinFET fins (with those fins being supported by the sidewall spacers). The openings below each of the fins are then filled with a dielectric material that serves to isolate the semiconductive materials of the fins from the substrate.

Abstract translation: 在第一半导体材料基板上沉积由第二半导体材料形成的上覆牺牲层。 在第一区域中，在牺牲层上形成第一半导体材料区域。 在第二区域中，在牺牲层上形成第二半导体材料区域。 图案化第一半导体材料区域以限定第一FinFET鳍片。 图案化第二半导体材料区域以限定第二FinFET鳍片。 翅片各自被盖和侧壁间隔物覆盖。 然后选择性地去除由第二半导体材料形成的牺牲层，以在第一和第二FinFET鳍片下面形成开口（这些鳍片由侧壁间隔件支撑）。 然后每个翅片下面的开口填充有用于将鳍片的半导体材料与衬底隔离的介电材料。

公开(公告)号：US09171757B2

公开(公告)日：2015-10-27

申请号：US14096515

申请日：2013-12-04

Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc. ,  COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Bruce B. Doris ,  Shom Ponoth ,  Prasanna Khare ,  Qing Liu ,  Nicolas Loubet ,  Maud Vinet

IPC: H01L21/336 ,  H01L21/76 ,  H01L21/425 ,  H01L21/768 ,  H01L21/762 ,  H01L29/06 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L21/76879 ,  H01L21/0217 ,  H01L21/76224 ,  H01L21/76283 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76897 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66568 ,  H01L29/66628 ,  H01L29/78609

Abstract: A shallow trench is formed to extend into a handle substrate of a semiconductor-on-insulator (SOI) layer. A dielectric liner stack of a dielectric metal oxide layer and a silicon nitride layer is formed in the shallow trench, followed by deposition of a shallow trench isolation fill portion. The dielectric liner stack is removed from above a top surface of a top semiconductor portion, followed by removal of a silicon nitride pad layer and an upper vertical portion of the dielectric metal oxide layer. A divot laterally surrounding a stack of a top semiconductor portion and a buried insulator portion is filled with a silicon nitride portion. Gate structures and source/drain structures are subsequently formed. The silicon nitride portion or the dielectric metal oxide layer functions as a stopping layer during formation of source/drain contact via holes, thereby preventing electrical shorts between source/drain contact via structures and the handle substrate.

Abstract translation: 形成浅沟槽以延伸到绝缘体上半导体（SOI）层的处理衬底中。 在浅沟槽中形成介质金属氧化物层和氮化硅层的电介质衬垫层，随后沉积浅沟槽隔离填充部分。 介电衬垫堆叠从顶部半导体部分的顶表面上方移除，随后除去介电金属氧化物层的氮化硅衬垫层和上部垂直部分。 横向围绕顶部半导体部分和掩埋绝缘体部分的堆叠的边角填充有氮化硅部分。 随后形成栅极结构和源极/漏极结构。 氮化硅部分或电介质金属氧化物层在形成源极/漏极接触通孔期间用作停止层，从而防止源极/漏极接触通孔结构和处理衬底之间的电短路。

公开(公告)号：US20150279994A1

公开(公告)日：2015-10-01

申请号：US14663843

申请日：2015-03-20

Applicant: STMICROELECTRONICS, INC.

Inventor： Pierre MORIN ,  Nicolas Loubet

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/088

CPC classification number: H01L29/7848 ,  H01L27/0886 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, and source and drain regions adjacent the channel region to generate shear and normal strain on the channel region. A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, source and drain regions adjacent the channel region, and a gate over the channel region. The fin may be canted with respect to the source and drain regions to generate shear and normal strain on the channel region.

Abstract translation: 半导体器件可以包括衬底，在衬底上方具有沟道区域的鳍，以及与沟道区相邻的源区和漏区，以在沟道区上产生剪切和正应变。 半导体器件可以包括衬底，在衬底上方的鳍片，其中具有沟道区域，与沟道区域相邻的源极和漏极区域以及沟道区域上的栅极。 翅片可以相对于源极和漏极区域倾斜以在沟道区域上产生剪切和正常应变。

公开(公告)号：US20150214338A1

公开(公告)日：2015-07-30

申请号：US14168175

申请日：2014-01-30

Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc. ,  Renesas Electronics Corporation

Inventor： Kangguo Cheng ,  Ali Khakifirooz ,  Nicolas Loubet ,  Shogo Mochizuki ,  Alexander Reznicek ,  Raghavasimhan Sreenivasan ,  Chun-Chen Yeh

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/225

CPC classification number: H01L29/66795 ,  H01L21/2254 ,  H01L21/30604 ,  H01L21/3065 ,  H01L29/7841 ,  H01L29/7848 ,  H01L29/785

Abstract: The present disclosure generally provides for a method of forming a FinFET with a silicon germanium (SiGe) stressor, in addition to a FinFET structure obtained from embodiments of the method. The method can include forming a semiconductor fin on a buried insulator layer; forming a gate structure on the semiconductor fin; forming a silicon germanium (SiGe) layer on the buried insulator layer, wherein the SiGe layer contacts the semiconductor fin; and heating the SiGe layer, wherein the heating diffuses germanium (Ge) into the semiconductor fin.

Abstract translation: 本公开通常提供了除了由该方法的实施例获得的FinFET结构之外还形成具有硅锗（SiGe）应力源的FinFET的方法。 该方法可以包括在掩埋绝缘体层上形成半导体鳍片; 在半导体鳍片上形成栅极结构; 在所述掩埋绝缘体层上形成硅锗层（SiGe），其中所述SiGe层接触所述半导体鳍片; 并加热SiGe层，其中加热使锗（Ge）扩散到半导体鳍片中。

公开(公告)号：US20150162434A1

公开(公告)日：2015-06-11

申请号：US14097570

申请日：2013-12-05

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Ronald Kevin Sampson

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L27/1211 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/26513 ,  H01L21/28035 ,  H01L21/3081 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/1083 ,  H01L29/167 ,  H01L29/4916 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor material is patterned to define elongated fins insulated from an underlying substrate. A polysilicon semiconductor material is deposited over and in between the elongated fins, and is patterned to define elongated gates extending to perpendicularly cross over the elongated fins at a transistor channel. Sidewall spacers are formed on side walls of the elongated gates. Portions of the elongated fins located between the elongated gates are removed, along with the underlying insulation, to expose the underlying substrate. One or more semiconductor material layers are then epitaxially grown from the underlying substrate at locations between the elongated gates. The one or more semiconductor material layers may include an undoped epi-layer and an overlying doped epi-layer. The epitaxial material defines a source or drain of the transistor.

公开(公告)号：US09018057B1

公开(公告)日：2015-04-28

申请号：US14048263

申请日：2013-10-08

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  Nicolas Loubet

IPC: H01L21/8238 ,  H01L29/66 ,  H01L21/762 ,  H01L29/10 ,  H01L29/78 ,  H01L29/49 ,  H01L29/165 ,  H01L21/02

CPC classification number: H01L29/7849 ,  H01L21/02532 ,  H01L21/2251 ,  H01L21/7624 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823892 ,  H01L21/84 ,  H01L21/845 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/7842 ,  H01L29/7848

Abstract: A method for forming a complementary metal oxide semiconductor (CMOS) semiconductor device includes providing a stressed silicon-on-insulator (sSOI) wafer comprising a stressed semiconductor layer having first and second laterally adjacent stressed semiconductor portions. The first stressed semiconductor portion defines a first active region. The second stressed semiconductor portion is replaced with an unstressed semiconductor portion. The unstressed semiconductor portion includes a first semiconductor material. The method further includes driving a second semiconductor material into the first semiconductor material of the unstressed semiconductor portion defining a second active region.

Abstract translation: 一种用于形成互补金属氧化物半导体（CMOS）半导体器件的方法包括提供包括具有第一和第二横向相邻应力半导体部分的应力半导体层的受应力的绝缘体上硅（sSOI）晶片。 第一应力半导体部分限定第一有源区。 第二应力半导体部分被未受应力的半导体部分代替。 未受应力的半导体部分包括第一半导体材料。 该方法还包括将第二半导体材料驱动到限定第二有源区的无应力半导体部分的第一半导体材料中。

公开(公告)号：US20150097244A1

公开(公告)日：2015-04-09

申请号：US14048244

申请日：2013-10-08

Applicant: STMicroelectronics, Inc.

Inventor： QING LIU ,  Nicolas Loubet

IPC: H01L27/12 ,  H01L21/84

CPC classification number: H01L27/0924 ,  H01L21/84 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/16 ,  H01L29/161 ,  H01L29/78603

Abstract: A method for making a semiconductor device includes forming a buried oxide stack on a semiconductor wafer. The buried oxide stack includes a first oxide layer, a nitride layer on the first oxide layer, and a second oxide layer on the nitride layer. A semiconductor layer is formed on the second oxide layer. First and second channel regions are formed in the semiconductor layer.

Abstract translation: 制造半导体器件的方法包括在半导体晶片上形成掩埋氧化层。 掩埋氧化物层包括第一氧化物层，第一氧化物层上的氮化物层和氮化物层上的第二氧化物层。 在第二氧化物层上形成半导体层。 第一和第二沟道区形成在半导体层中。