中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

63 records (took 0.023 seconds)

    Semiconductor devices having penetration vias with portions having decreasing widths
    52.
    发明授权
    Semiconductor devices having penetration vias with portions having decreasing widths 有权

    公开(公告)号：US11664316B2

    公开(公告)日：2023-05-30

    申请号：US16849085

    申请日：2020-04-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hakseung Lee ,  Jinnam Kim ,  Hyoukyung Cho ,  Taeseong Kim ,  Kwangjin Moon

    IPC: H01L23/538

    CPC classification number: H01L23/5384 ,  H01L23/5385 ,  H01L2224/08146

    Abstract: A semiconductor device may include a first semiconductor substrate having a first surface and a second surface opposite to each other, a first circuit layer provided on the first surface of the first semiconductor substrate, a connection pad provided on the second surface of the first semiconductor substrate, and a first penetration via and a second penetration via penetrating the first semiconductor substrate and at least a portion of the first circuit layer. The first penetration via and the second penetration via may be provided in a first penetration hole and a second penetration hole, respectively. Each of the first and second penetration holes may include a first portion, a second portion, and a third portion. A width of the first portion of the first penetration hole may be smaller than a width of the first portion of the second penetration hole.

    INTEGRATED CIRCUIT DEVICE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME
    53.
    发明申请
    INTEGRATED CIRCUIT DEVICE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME 有权

    公开(公告)号：US20220367320A1

    公开(公告)日：2022-11-17

    申请号：US17560495

    申请日：2021-12-23

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hojin Lee ,  Kwangjin Moon ,  Seungha Oh

    IPC: H01L23/48 ,  H01L21/768 ,  H01L25/065 ,  H01L23/498 ,  H01L23/00

    Abstract: An integrated circuit device includes a semiconductor substrate having a first surface and a second surface opposite to the first surface, a first insulating layer on the first surface of the semiconductor substrate, an electrode landing pad positioned on the first surface of the semiconductor substrate and having a sidewall surrounded by the first insulating layer, a top surface apart from the first surface of the semiconductor substrate, and a bottom surface opposite to the top surface, and a through-electrode configured to penetrate through the semiconductor substrate and contact the top surface of the electrode landing pad, wherein a horizontal width of the top surface of the electrode landing pad is less than a horizontal width of the bottom surface of the electrode landing pad and greater than a horizontal width of a bottom surface of the through-electrode in contact with the top surface of the electrode landing pad.

    Semiconductor device
    55.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US11342221B2

    公开(公告)日：2022-05-24

    申请号：US16741187

    申请日：2020-01-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jaewon Hwang ,  Jinnam Kim ,  Kwangjin Moon ,  Kunsang Park ,  Myungjoo Park

    IPC: H01L21/768 ,  H01L21/02 ,  H01L21/306

    Abstract: Aspects of the present disclosure are related to a semiconductor device that includes a crystalline substrate having a first surface and a second surface vertically opposite each other and an insulating layer disposed on the first surface of the crystalline substrate. The device may also include an etch stop layer interposed between and contacting the crystalline substrate and the insulating layer and a conductive through via structure penetrating the crystalline substrate and the insulating layer. The device may also include an insulating separation layer disposed horizontally adjacent to the conductive through via structure, and having an inner wall and an outer wall. The insulating separation layer may include a first portion disposed between the conductive through via structure and the crystalline substrate, and a second portion disposed between the conductive through via structure and the etch stop layer.

    Semiconductor devices including through vias and methods of fabricating the same
    57.
    发明授权
    Semiconductor devices including through vias and methods of fabricating the same 有权

    公开(公告)号：US11295981B2

    公开(公告)日：2022-04-05

    申请号：US16734456

    申请日：2020-01-06

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yi Koan Hong ,  Taeseong Kim ,  Kwangjin Moon

    IPC: H01L21/02 ,  H01L21/768

    Abstract: Disclosed are semiconductor devices including through vias and methods of fabricating the same. The methods may include forming a first structure including a metal pattern and a second structure on the first structure. The metal pattern includes an upper surface facing the second structure. The methods may also include etching the second structure to form a via hole exposing the metal pattern, oxidizing a first etch residue in the via hole to convert the first etch residue into an oxidized first etch residue, and removing the oxidized first etch residue. After removing the oxidized first etch residue, the upper surface of the metal pattern may include a first portion that includes a recess and has a first surface roughness and a second portion that is different from the first portion and has a second surface roughness. The first surface roughness may be greater than the second surface roughness.

    Semiconductor device
    58.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US11004814B2

    公开(公告)日：2021-05-11

    申请号：US16244304

    申请日：2019-01-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ju-il Choi ,  Kwangjin Moon ,  Sujeong Park ,  JuBin Seo ,  Jin Ho An ,  Dong-chan Lim ,  Atsushi Fujisaki

    IPC: H01L23/00

    Abstract: Disclosed is a semiconductor device including a conductive pattern on a substrate, a passivation layer on the substrate and including an opening that partially exposes the conductive pattern, and a pad structure in the opening of the passivation layer and connected to the conductive pattern. The pad structure includes a first metal layer that fills the opening of the passivation layer and has a width greater than that of the opening, and a second metal layer on the first metal layer. The first metal layer has a first thickness at an outer wall of the first metal layer, a second thickness on a top surface of the passivation layer, and a third thickness on a top surface of the conductive pattern. The second thickness is greater than the first thickness, and the third thickness is greater than the second thickness.

    SEMICONDUCTOR DEVICES
    60.
    发明申请
    SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20210057371A1

    公开(公告)日：2021-02-25

    申请号：US16854114

    申请日：2020-04-21

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jaehyung Park ,  Seokho Kim ,  Hoonjoo Na ,  Kwangjin Moon ,  Kyuha Lee ,  Joohee Jang

    IPC: H01L23/00 ,  H01L27/30 ,  H01L27/28

    Abstract: A semiconductor device includes a first adsorption layer, a first bonding layer, a second bonding layer, and a second adsorption layer stacked on a first substrate, and a conductive pattern structure penetrating through the first adsorption layer, the first bonding layer, the second bonding layer and the second adsorption layer. The first and second bonding layers are in contact with each other, and each of the first and second adsorption layers includes a low-K dielectric material.

Patent Agency Ranking