公开(公告)号：US07733997B2

公开(公告)日：2010-06-08

申请号：US11486581

申请日：2006-07-14

申请人： Tin H. Lai ,  Wilson Wong ,  Sergey Shumarayev ,  Simardeep Maangat

发明人： Tin H. Lai ,  Wilson Wong ,  Sergey Shumarayev ,  Simardeep Maangat

IPC分类号： H04B1/10

CPC分类号： H04B7/005 ,  H04L25/03006 ,  H04L25/061

摘要： Systems and methods for adjusting a signal received from a communication path are disclosed. A receiver can receive a signal from a communication path which attenuates at least some frequency components of the signal. The receiver can include an equalization block that adjusts at least some of the frequency content of the received signal, a signal normalization block that provides a normalized signal amplitude and/or a normalized edge slope, and a control block. In one embodiment, the control block controls frequency adjustment in the equalization block for high frequencies. For low frequency adjustment, user-programmable parameters control the normalized signal amplitude in the signal normalization block and the low frequency adjustment in the equalization block.

摘要翻译： 公开了一种用于调整从通信路径接收的信号的系统和方法。 接收机可以接收来自衰减信号的至少一些频率分量的通信路径的信号。 接收机可以包括调整接收信号的频率内容中的至少一些的均衡块，提供归一化信号幅度和/或归一化边沿斜率的信号归一化块以及控制块。 在一个实施例中，控制块控制用于高频的均衡块中的频率调整。 对于低频调整，用户可编程参数控制信号归一化块中的归一化信号幅度和均衡块中的低频调整。

公开(公告)号：US20060220681A1

公开(公告)日：2006-10-05

申请号：US11098832

申请日：2005-04-04

申请人： Wilson Wong ,  Tim Hoang ,  Sergey Shumarayev ,  Rakesh Patel ,  Simardeep Maangat

发明人： Wilson Wong ,  Tim Hoang ,  Sergey Shumarayev ,  Rakesh Patel ,  Simardeep Maangat

IPC分类号： H03K19/094

CPC分类号： H03K19/017545

摘要： Circuitry and methods are provided for an LVDS-like transmitter that may be able to DC couple to a receiver having a CML termination scheme. Replacing the common mode voltage source of an LVDS transmitter with a resistive pulldown to ground may allow the transmitter to interface in a DC coupled fashion with a CML receiver. Further, the resistive pulldown may be programmable. This LVDS-like transmitter may be able to support a wider customer base by allowing it to DC couple to a wider range of termination voltage levels, such as CML termination voltage levels.

摘要翻译： 为能够将DC耦合到具有CML终止方案的接收机的类似LVDS的发射机提供电路和方法。 将具有电阻下拉到地的LVDS发射机的共模电压源替换可允许发射机以直流耦合方式与CML接收器接口。 此外，电阻下拉可以是可编程的。 这种类似LVDS的发射机可能能够通过允许其将DC耦合到更广泛的终止电压电平范围（例如CML终止电压电平）来支持更广泛的客户群。

公开(公告)号：US08081723B1

公开(公告)日：2011-12-20

申请号：US12082343

申请日：2008-04-09

申请人： Weiqi Ding ,  Sergey Shumarayev ,  Wilson Wong ,  Thungoc M. Tran

发明人： Weiqi Ding ,  Sergey Shumarayev ,  Wilson Wong ,  Thungoc M. Tran

IPC分类号： H04L7/00

CPC分类号： H04L7/048 ,  H04L1/205 ,  H04L7/033

摘要： Methods and apparatus for determining at least part of the width of the eye of a high-speed serial data signal use clock and data recovery circuitry operating on that signal to produce a first clock signal having a first phase relationship to the data signal. The first clock signal is used to produce a second clock signal whose phase can be controllably shifted relative to the first phase. The second clock signal is used to sample the data signal with different amounts of phase shift, e.g., until error checking circuitry detects that data errors in the resulting sample exceed an acceptable threshold for such errors. The amount(s) of phase shift that caused exceeding the threshold can be used as a basis for a measurement of eye width.

摘要翻译： 用于确定高速串行数据信号的眼睛的至少部分宽度的方法和装置使用在该信号上操作的时钟和数据恢复电路，以产生与数据信号具有第一相位关系的第一时钟信号。 第一时钟信号用于产生第二时钟信号，其相位可相对于第一相位被可控地偏移。 第二时钟信号用于以不同量的相移对数据信号进行采样，例如直到错误检查电路检测到所得样本中的数据错误超过这种错误的可接受的阈值。 引起超过阈值的相移量可用作测量眼睛宽度的基础。

公开(公告)号：US08933751B1

公开(公告)日：2015-01-13

申请号：US13475678

申请日：2012-05-18

申请人： Wilson Wong ,  Weiqi Ding ,  Shuxian Chen ,  Simardeep Maangat ,  Albert Ratnakumar

发明人： Wilson Wong ,  Weiqi Ding ,  Shuxian Chen ,  Simardeep Maangat ,  Albert Ratnakumar

IPC分类号： H03F3/45 ,  H01G4/40 ,  H03F1/56

CPC分类号： H01G4/40 ,  H01G17/00 ,  H03F1/56

摘要： A first trimming capacitor having a first terminal and a second terminal is coupled in parallel between a first terminal and a second terminal of a first capacitor. The first trimming capacitor comprises a first plurality of switched capacitors having different capacitances coupled in parallel. Each of the switched capacitors comprises a switch capacitor and a switch coupled in series. In an illustrative application the first capacitor and the first trimming capacitor are coupled between an output terminal of an operational amplifier (op-amp) and an inverting input terminal of the op-amp. A second capacitor and a second trimming capacitor similar to the first capacitor and the first trimming capacitor are coupled between an input and the inverting input terminal of the op-amp.

摘要翻译： 具有第一端子和第二端子的第一微调电容器并联耦合在第一电容器的第一端子和第二端子之间。 第一微调电容器包括具有并联耦合的不同电容的第一多个开关电容器。 每个开关电容器包括开关电容器和串联耦合的开关。 在说明性应用中，第一电容器和第一微调电容器耦合在运算放大器（运算放大器）的输出端和运算放大器的反相输入端之间。 类似于第一电容器和第一微调电容器的第二电容器和第二微调电容器耦合在运算放大器的输入端和反相输入端子之间。

公开(公告)号：US07702011B2

公开(公告)日：2010-04-20

申请号：US11361192

申请日：2006-02-23

申请人： Thungoc Tran ,  Sergey Yuryevich Shumarayev ,  Simardeep Maangat ,  Wilson Wong ,  Rakesh Patel

发明人： Thungoc Tran ,  Sergey Yuryevich Shumarayev ,  Simardeep Maangat ,  Wilson Wong ,  Rakesh Patel

IPC分类号： H03H7/30

CPC分类号： H04L1/243 ,  H04L25/03878

摘要： Serial data signal receiver circuitry for inclusion on a PLD includes a plurality of equalizer circuits that are connected in series and that are individually controllable so that collectively they can compensate for a wide range of possible input signal attenuation characteristics. Other circuit features may be connected in relation to the equalizer circuits to give the receiver circuitry other capabilities. For example, these other features may include various types of loop-back test circuits, controllable termination resistance, controllable common mode voltage, and a controllable threshold for detection of an input signal. Various aspects of control of the receiver circuitry may be programmable.

摘要翻译： 用于包含在PLD中的串行数据信号接收器电路包括串联连接并且可单独控制的多个均衡器电路，使得它们可以统一地补偿宽范围的可能的输入信号衰减特性。 其他电路特征可以相对于均衡器电路连接以给予接收机电路其他能力。 例如，这些其他特征可以包括各种类型的环回测试电路，可控终端电阻，可控共模电压以及用于检测输入信号的可控阈值。 接收器电路的控制的各个方面可以是可编程的。

公开(公告)号：US07639993B1

公开(公告)日：2009-12-29

申请号：US11295391

申请日：2005-12-05

申请人： Sergey Yuryevich Shumarayev ,  Rakesh Patel ,  William Bereza ,  Wilson Wong ,  Tim Tri Hoang

发明人： Sergey Yuryevich Shumarayev ,  Rakesh Patel ,  William Bereza ,  Wilson Wong ,  Tim Tri Hoang

IPC分类号： H04B1/04

CPC分类号： H04L7/033

摘要： The various components of transceiver circuitry on an integrated circuit are put together in various ways for purposes of being supplied with power to help prevent noise propagation between the groups. In the case of multi-channel transceiver circuitry there can be various amounts of power supply sharing between similar groups in multiple channels.

摘要翻译： 集成电路中的收发器电路的各种组件以各种方式放在一起，以便被提供电力以帮助防止组之间的噪声传播。 在多通道收发器电路的情况下，可以在多个通道中的类似组之间存在各种数量的电源共享。

公开(公告)号：US09246715B1

公开(公告)日：2016-01-26

申请号：US12432136

申请日：2009-04-29

申请人： Allen Chan ,  Wilson Wong ,  Tim Tri Hoang

发明人： Allen Chan ,  Wilson Wong ,  Tim Tri Hoang

IPC分类号： H03K19/094 ,  H04L25/02 ,  H03K19/003

CPC分类号： H04L25/0272 ,  H03K19/00315 ,  H03K19/00361

摘要： A pre-emphasis circuitry that includes (1) a pre-emphasis voltage variation compensation (PVVC) engine having a transition detection circuit and (2) a compensation driver coupled to the PVVC engine is described. In one embodiment, the compensation driver reduces data dependent voltage variations in pre-emphasis provided by the pre-emphasis circuitry. In one embodiment, in response to a predetermined data pattern detected by the PVVC engine, the compensation driver provides an additional boost to performance critical capacitive nodes of the pre-emphasis circuitry. The additional boost causes the performance critical capacitive nodes to charge or discharge more rapidly. In one embodiment, the PVVC engine further includes a digital finite impulse response (FIR) filter coupled to the transition detection circuit. Also, in one embodiment, the PVVC engine further includes an FIR delay circuit coupled to the digital FIR filter and a synchronizer circuit coupled to the digital FIR filter and the FIR delay circuit, where the FIR delay circuit introduces latency to match-delay produced by the transition detection circuit and the synchronizer circuit synchronizes data to be sent to the main driver, the pre-emphasis driver, and the compensation driver.

摘要翻译： 一种预加重电路，其包括（1）具有转移检测电路的预加重电压变化补偿（PVVC）引擎和（2）耦合到PVVC引擎的补偿驱动器。 在一个实施例中，补偿驱动器减少由预加重电路提供的预加重中的数据相关电压变化。 在一个实施例中，响应于由PVVC引擎检测到的预定数据模式，补偿驱动器为预加重电路的性能关键电容性节点提供额外的提升。 额外的升压会导致性能关键的电容性节点更快地充电或放电。 在一个实施例中，PVVC引擎还包括耦合到转换检测电路的数字有限脉冲响应（FIR）滤波器。 此外，在一个实施例中，PVVC引擎还包括耦合到数字FIR滤波器的FIR延迟电路和耦合到数字FIR滤波器和FIR延迟电路的同步器电路，其中FIR延迟电路将等待时间延迟到由 转换检测电路和同步器电路将要发送到主驱动器，预加重驱动器和补偿驱动器的数据同步。

公开(公告)号：US08189729B2

公开(公告)日：2012-05-29

申请号：US11329197

申请日：2006-01-09

申请人： Tim Tri Hoang ,  Sergey Yuryevich Shumarayev ,  Wilson Wong ,  Rakesh Patel

发明人： Tim Tri Hoang ,  Sergey Yuryevich Shumarayev ,  Wilson Wong ,  Rakesh Patel

IPC分类号： H04L7/00

CPC分类号： H03L7/087 ,  H03K19/17732 ,  H03K19/17744 ,  H03L7/10 ,  H04L7/0004 ,  H04L7/033

摘要： Wide range and dynamically reprogrammable CDR architecture recovers an embedded clock signal from serial input data with a wide range of operating frequencies. In order to support a wide range of data rates, the CDR architecture includes multiple operating parameters. These parameters include various pre/post divider settings, charge pump currents, loop-filter and bandwidth selections, and VCO gears. The parameters may be dynamically reprogrammed without powering down the circuitry or PLD. This allows the CDR circuitry to switch between various standards and protocols on-the-fly.

摘要翻译： 宽范围和动态可重新编程的CDR架构从具有广泛工作频率的串行输入数据中恢复嵌入式时钟信号。 为了支持广泛的数据速率，CDR架构包括多个操作参数。 这些参数包括各种前/后分频器设置，电荷泵电流，环路滤波器和带宽选择以及VCO齿轮。 可以在不关闭电路或PLD的情况下动态重新编程参数。 这允许CDR电路在各种标准和协议之间进行即时切换。

公开(公告)号：US07590207B1

公开(公告)日：2009-09-15

申请号：US11256346

申请日：2005-10-20

申请人： Sergey Y Shumarayev ,  Rakesh H Patel ,  Wilson Wong ,  Tim Tri Hoang ,  William Bereza

发明人： Sergey Y Shumarayev ,  Rakesh H Patel ,  Wilson Wong ,  Tim Tri Hoang ,  William Bereza

IPC分类号： H04L7/00

CPC分类号： H03L7/087 ,  H04J3/0688 ,  H04L7/033

摘要： A serial interface for a programmable logic device can be used as a conventional high-speed quad interface, but also allows an individual channel, if not otherwise being used, to be programmably configured as a loop circuit (e.g., a phase-locked loop). This is accomplished by disabling the data loop of clock-data recovery circuitry in the channel, and reconfiguring the reference loop to operate as a loop circuit. In addition, instead of providing a high-speed quad interface having four channels and one or more clock management units (CMUs), a more flexible interface having five or more channels can be provided, and when it is desired to use the interface as a high-speed quad interface, one or more channels can be configured as loop circuits to function as CMUs.

摘要翻译： 用于可编程逻辑器件的串行接口可以用作传统的高速四边形接口，但是也允许单独的通道（如果不另外使用）被可编程地配置为环路电路（例如，锁相环） 。 这是通过禁用通道中的时钟数据恢复电路的数据循环来实现的，并且重新配置参考环路以用作循环电路。 此外，不是提供具有四个通道的高速四边形接口和一个或多个时钟管理单元（CMU），而是可以提供具有五个或更多个通道的更灵活的接口，并且当希望将接口用作 高速四通道接口，一个或多个通道可以配置为循环电路，用作CMU。

公开(公告)号：US08416845B1

公开(公告)日：2013-04-09

申请号：US11484285

申请日：2006-07-11

申请人： Wilson Wong ,  Sergey Yuryevich Shumarayev ,  Rakesh Patel ,  Tim Tri Hoang

发明人： Wilson Wong ,  Sergey Yuryevich Shumarayev ,  Rakesh Patel ,  Tim Tri Hoang

IPC分类号： H03H7/30 ,  H03H7/40 ,  H03K5/159

CPC分类号： H04L25/03057 ,  H03K5/1532

摘要： Methods and circuits for automatic adjustment of equalization are presented that improve the quality of equalization for input signals with varying amplitudes. The methods and circuits may be used in Decision Feedback Equalization (DFE) circuits to maintain a constant equalization boost amplitude despite variations in input signal amplitude. The equalization circuitry measures the amplitude of the equalization input signal and computes tap coefficients to maintain a desired level of boost amplitude. Tap coefficients may be automatically adjusted by the equalization circuitry.

摘要翻译： 提出了用于自动调整均衡的方法和电路，其提高具有变化幅度的输入信号的均衡质量。 方法和电路可以用于判决反馈均衡（DFE）电路中，以维持恒定的均衡提升幅度，尽管输入信号幅度有变化。 均衡电路测量均衡输入信号的幅度并计算抽头系数以维持期望的升压幅度。 抽头系数可以由均衡电路自动调整。