公开(公告)号：US09246015B2

公开(公告)日：2016-01-26

申请号：US12892044

申请日：2010-09-28

申请人： Tzu-Hsuan Hsu ,  Yen-Hao Shih ,  Chia-Wei Wu

发明人： Tzu-Hsuan Hsu ,  Yen-Hao Shih ,  Chia-Wei Wu

IPC分类号： H01L29/66 ,  H01L29/792 ,  H01L27/115 ,  H01L29/423 ,  H01L27/12

CPC分类号： H01L29/792 ,  H01L27/115 ,  H01L27/11568 ,  H01L27/1203 ,  H01L29/42352

摘要： A vertical channel transistor structure is provided. The structure includes a substrate, a channel, a cap layer, a charge trapping layer, a source and a drain. The channel is formed in a fin-shaped structure protruding from the substrate. The cap layer is deposited on the fin-shaped structure. The cap layer and the fin-shaped structure have substantially the same width. The charge trapping layer is deposited on the cap layer and on two vertical surfaces of the fin-shaped structure. The gate is deposited on the charge trapping layer and on two vertical surfaces of the fin-shaped structure. The source and the drain are respectively positioned on two sides of the fin-shaped structure and opposite the gate.

摘要翻译： 提供了垂直沟道晶体管结构。 该结构包括基板，通道，盖层，电荷捕获层，源极和漏极。 通道形成为从基板突出的鳍状结构。 盖层沉积在鳍状结构上。 盖层和鳍状结构具有基本上相同的宽度。 电荷俘获层沉积在盖层上和鳍状结构的两个垂直表面上。 栅极沉积在电荷捕获层上并在鳍状结构的两个垂直表面上沉积。 源极和漏极分别位于鳍状结构的两侧并与栅极相对。

公开(公告)号：US08816423B2

公开(公告)日：2014-08-26

申请号：US13584366

申请日：2012-08-13

申请人： Erh-Kun Lai ,  Yen-Hao Shih

发明人： Erh-Kun Lai ,  Yen-Hao Shih

IPC分类号： H01L29/792

CPC分类号： H01L27/11582 ,  H01L27/11529 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

摘要： A semiconducting multi-layer structure comprising a plurality of first conductive layers, a plurality of first insulating layers and a second conductive layer is disclosed. The first conductive layers are separately disposed. Each of the first conductive layers has an upper surface, a bottom surface opposite to the upper surface and a lateral surface. The first insulating layers surround the peripherals of the first conductive layers. Each of the first insulating layers covers at least a part of the upper surface of each of the first conductive layers, at least a part of the bottom surface of each of the first conductive layers and the two lateral surface of each of the first conductive layers. The second conductive layer covers the first conductive layers and the first insulating layers.

摘要翻译： 公开了一种包括多个第一导电层，多个第一绝缘层和第二导电层的半导体多层结构。 第一导电层分开设置。 每个第一导电层具有上表面，与上表面相对的底表面和侧表面。 第一绝缘层围绕第一导电层的外围设备。 每个第一绝缘层覆盖每个第一导电层的上表面的至少一部分，每个第一导电层的底表面的至少一部分和每个第一导电层的两个侧表面 。 第二导电层覆盖第一导电层和第一绝缘层。

公开(公告)号：US20140140131A1

公开(公告)日：2014-05-22

申请号：US13681133

申请日：2012-11-19

申请人： Teng-Hao Yeh ,  Yen-Hao Shih ,  Yan-Ru Chen

发明人： Teng-Hao Yeh ,  Yen-Hao Shih ,  Yan-Ru Chen

IPC分类号： H01L29/788 ,  G11C5/06 ,  G11C16/04 ,  H01L21/28

CPC分类号： G11C5/06 ,  G11C5/063 ,  G11C16/0483 ,  G11C2213/71 ,  H01L21/28282 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/7926

摘要： A device on an integrated circuit includes a stack of alternating semiconductor lines and insulating lines, and a gate structure over the stack of semiconductor lines. The gate structure includes a vertical portion adjacent the stack on the at least one side, and horizontal extension portions between the semiconductor lines. Sides of the insulating lines can be recessed relative to sides of the semiconductor lines, so at least one side of the stack includes recesses between semiconductor lines. The horizontal extension portions can be in the recesses. The horizontal extension portions have inside surfaces adjacent the sides of the insulating lines, and outside surfaces that can be flush with the sides of the semiconductor lines. The device may include a second gate structure spaced away from the first mentioned gate structure, and an insulating element between horizontal extension portions of the second gate structure and the first mentioned gate structure.

摘要翻译： 集成电路中的器件包括交替的半导体线路和绝缘线路的堆叠以及在半导体线路堆叠上的栅极结构。 栅极结构包括在至少一个侧面上与堆叠相邻的垂直部分和半导体线之间的水平延伸部分。 绝缘线的边可以相对于半导体线的侧面凹陷，因此堆叠的至少一侧包括半导体线之间的凹槽。 水平延伸部分可以在凹槽中。 水平延伸部具有与绝缘线的侧面相邻的内表面以及可与半导体线的侧面齐平的外表面。 器件可以包括与第一提到的栅极结构间隔开的第二栅极结构，以及在第二栅极结构的水平延伸部分和第一个提到的栅极结构之间的绝缘元件。

公开(公告)号：US08374019B2

公开(公告)日：2013-02-12

申请号：US12985253

申请日：2011-01-05

申请人： Chao-I Wu ,  Yen-Hao Shih ,  Ming-Hsiu Lee

发明人： Chao-I Wu ,  Yen-Hao Shih ,  Ming-Hsiu Lee

IPC分类号： G11C11/00

CPC分类号： H01L45/06 ,  G11C11/005 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C14/00 ,  G11C2013/0083 ,  G11C2013/0092 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1641

摘要： A memory device including programmable resistance memory cells, including electrically pre-stressed target memory cells. The pre-stressed target memory cells have one of a lower voltage transition threshold, a shorter duration set interval and a longer reset state retention characteristic. Biasing circuitry is included on the device configured to control the pre-stressing operations, and to apply read, set and reset operations that can be modified for the pre-stressed memory cells.

摘要翻译： 一种包括可编程电阻存储单元的存储器件，包括电预应力目标存储单元。 预应力目标存储单元具有较低电压转变阈值，较短持续时间设定间隔和较长复位状态保持特性之一。 设备上包括偏置电路，用于控制预应力操作，以及应用对预应力存储单元进行修改的读取，置位和复位操作。

公开(公告)号：US20120193595A1

公开(公告)日：2012-08-02

申请号：US13076169

申请日：2011-03-30

申请人： Huai-Yu Cheng ,  Chieh-Fang Chen ,  Hsiang-Lan Lung ,  Yen-Hao Shih ,  Simone Raoux ,  Matthew J. Breitwisch

发明人： Huai-Yu Cheng ,  Chieh-Fang Chen ,  Hsiang-Lan Lung ,  Yen-Hao Shih ,  Simone Raoux ,  Matthew J. Breitwisch

IPC分类号： H01L45/00 ,  C23C14/14 ,  C23C14/34

CPC分类号： H01L47/00 ,  C23C14/06 ,  C23C14/0623 ,  C23C14/3414 ,  H01L21/06 ,  H01L27/24 ,  H01L45/144 ,  H01L45/1625

摘要： A layer of phase change material with silicon or another semiconductor, or a silicon-based or other semiconductor-based additive, is formed using a composite sputter target including the silicon or other semiconductor, and the phase change material. The concentration of silicon or other semiconductor is more than five times greater than the specified concentration of silicon or other semiconductor in the layer being formed. For silicon-based additive in GST-type phase change materials, sputter target may comprise more than 40 at % silicon. Silicon-based or other semiconductor-based additives can be formed using the composite sputter target with a flow of reactive gases, such as oxygen or nitrogen, in the sputter chamber during the deposition.

摘要翻译： 使用包括硅或其它半导体的复合溅射靶和相变材料形成具有硅或另一半导体或硅基或其它基于半导体的添加剂的相变材料层。 硅或其他半导体的浓度比正在形成的层中规定浓度的硅或其它半导体的浓度高五倍以上。 对于GST型相变材料中的硅基添加剂，溅射靶可以包含超过40at％的硅。 可以在沉积期间使用复合溅射靶在溅射室中形成具有诸如氧或氮的反应气体流的硅基或其它基于半导体的添加剂。

公开(公告)号：US08026136B2

公开(公告)日：2011-09-27

申请号：US11964322

申请日：2007-12-26

申请人： Yen-Hao Shih ,  Min-Ta Wu ,  Shih-Chin Lee ,  Jung-Yu Hsieh ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

发明人： Yen-Hao Shih ,  Min-Ta Wu ,  Shih-Chin Lee ,  Jung-Yu Hsieh ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

IPC分类号： H01L21/8238 ,  H01L21/311

CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L29/513 ,  H01L29/518

摘要： Memory cells comprising: a semiconductor substrate having at least two source/drain regions separated by a channel region; a charge-trapping structure disposed above the channel region; and a gate disposed above the charge-trapping structure; wherein the charge-trapping structure comprises a bottom insulating layer, a first charge-trapping layer, and a second charge-trapping layer, wherein an interface between the bottom insulating layer and the substrate has a hydrogen concentration of less than about 3×1011/cm−2, and methods for forming such memory cells.

摘要翻译： 存储单元包括：半导体衬底，具有由沟道区分开的至少两个源极/漏极区域; 设置在通道区域上方的电荷捕获结构; 以及设置在电荷捕获结构上方的栅极; 其中所述电荷捕获结构包括底部绝缘层，第一电荷俘获层和第二电荷俘获层，其中所述底部绝缘层和所述基底之间的界面的氢浓度小于约3×1011 / cm -2，以及形成这种记忆单元的方法。

公开(公告)号：US07911856B2

公开(公告)日：2011-03-22

申请号：US12471411

申请日：2009-05-25

申请人： Ming-Hsiu Lee ,  Yen-Hao Shih

发明人： Ming-Hsiu Lee ,  Yen-Hao Shih

IPC分类号： G11C7/00

CPC分类号： G11C13/0023 ,  G11C13/00 ,  G11C13/0004 ,  G11C17/06 ,  G11C17/16 ,  G11C2213/71 ,  G11C2213/77 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/1203 ,  H01L29/66833 ,  H01L29/792

摘要： A method of accessing memory cells is disclosed. A first signal is sent to at least one layer select transistor. The at least one layer select transistor is activated based on the first signal. Signals are communicated to or from one or more memory cells based on the activated at least layer select transistor.

摘要翻译： 公开了访问存储器单元的方法。 第一信号被发送到至少一个层选择晶体管。 基于第一信号激活至少一个层选择晶体管。 基于激活的至少层选择晶体管将信号传送到或来自一个或多个存储器单元。

公开(公告)号：US07824991B2

公开(公告)日：2010-11-02

申请号：US11334249

申请日：2006-01-18

申请人： Yen-Hao Shih ,  Shih-Chin Lee

发明人： Yen-Hao Shih ,  Shih-Chin Lee

IPC分类号： H01L21/336 ,  H01L21/31

CPC分类号： H01L21/28282 ,  H01L29/517 ,  H01L29/518 ,  Y10S438/954

摘要： A MOSFET fabrication process comprises nitridation of the dielectric silicon interface so that silicon-dangling bonds are connected with nitrogen atoms creating silicon—nitrogen bonds, which are stronger than silicon-hydrogen bonds. A tunnel dielectric is formed on the substrate. A nitride layer is then formed over the tunnel dielectric layer. The top of the nitride layer is then converted to an oxide and the interface between the substrate and the tunnel dielectric is nitrided simultaneously with conversion of the nitride layer to oxide.

摘要翻译： MOSFET制造工艺包括电介质硅界面的氮化，使得硅 - 悬挂键与氮原子连接，产生比硅 - 氢键更强的硅 - 氮键。 在基板上形成隧道电介质。 然后在隧道介电层上形成氮化物层。 然后将氮化物层的顶部转化为氧化物，并且衬底和隧道电介质之间的界面同时氮化氮化物层与氧化物的氮化。

公开(公告)号：US07763935B2

公开(公告)日：2010-07-27

申请号：US11159269

申请日：2005-06-23

申请人： Yen-Hao Shih ,  Shih-Chin Lee ,  Jung-Yu Hsieh ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

发明人： Yen-Hao Shih ,  Shih-Chin Lee ,  Jung-Yu Hsieh ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

IPC分类号： H01L21/336

CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/66833

摘要： A method of fabricating a non-volatile memory device at least comprises steps as follows. First, a substrate on which a bottom dielectric layer is formed is provided. Then, impurities are introduced through the bottom dielectric layer to the substrate, so as to form a plurality of spaced doped regions on the substrate. The structure is thermally annealed for pushing the spaced doped regions to diffuse outwardly. After annealing, a charge trapping layer is formed on the bottom dielectric layer, and a top dielectric layer is formed on the charge trapping layer. Finally, a gate structure (such as a polysilicon layer and a silicide) is formed on the top dielectric layer.

摘要翻译： 一种制造非易失性存储器件的方法至少包括以下步骤。 首先，提供形成有底部电介质层的基板。 然后，通过底部电介质层将杂质引入衬底，以在衬底上形成多个间隔开的掺杂区域。 该结构被热退火以推动间隔开的掺杂区域向外扩散。 退火后，在底部电介质层上形成电荷捕捉层，在电荷捕获层上形成顶部电介质层。 最后，在顶部电介质层上形成栅极结构（如多晶硅层和硅化物）。

公开(公告)号：US20080290397A1

公开(公告)日：2008-11-27

申请号：US11753850

申请日：2007-05-25

申请人： Tzu-Hsuan Hsu ,  Ming-Hsiang Hsueh ,  Yen-Hao Shih ,  Chia-Wei Wu

发明人： Tzu-Hsuan Hsu ,  Ming-Hsiang Hsueh ,  Yen-Hao Shih ,  Chia-Wei Wu

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L21/28282 ,  H01L29/42352 ,  H01L29/66833 ,  H01L29/792

摘要： A memory cell is disposed on a substrate having plurality of isolation structures that define at least a fin structure in the substrate, wherein the surface of the fin structure is higher than that of the isolation structures. The memory cell includes a gate, a charge trapping structure, a protection layer and two source/drain regions. The gate is disposed on the substrate,and straddled the fin structure. The charge trapping structure is disposed between the gate and the fin structure. The protection layer is disposed between the upper portion of the fin structure and the gate separating the charge trapping structure. The source/drain regions are disposed in the fin structure at both sides of the gate.

摘要翻译： 存储单元设置在具有多个隔离结构的衬底上，所述隔离结构在衬底中至少限定翅片结构，其中鳍结构的表面高于隔离结构的表面。 存储单元包括栅极，电荷俘获结构，保护层和两个源极/漏极区域。 栅极设置在基板上，并跨接在翅片结构上。 电荷捕获结构设置在栅极和鳍结构之间。 保护层设置在翅片结构的上部和分离电荷捕获结构的栅极之间。 源极/漏极区域设置在栅极两侧的鳍结构中。