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51.发明申请REINFORCED VIA FARM INTERCONNECT STRUCTURE, A METHOD OF FORMING A REINFORCED VIA FARM INTERCONNECT STRUCTURE AND A METHOD OF REDESIGNING AN INTEGRATED CIRCUIT CHIP TO INCLUDE SUCH A REINFORCED VIA FARM INTERCONNECT STRUCTURE 审中-公开通过农业互连结构增强，通过农业互连结构形成增强的方法以及重新组合集成电路芯片以包括通过农业互连结构增强的方法公开(公告)号：US20120261813A1
公开(公告)日：2012-10-18
申请号：US13087449
申请日：2011-04-15
申请人： Felix P. Anderson , Timothy H. Daubenspeck , Jeffrey P. Gambino , Donald R. Letourneau , Thomas L. McDevitt
发明人： Felix P. Anderson , Timothy H. Daubenspeck , Jeffrey P. Gambino , Donald R. Letourneau , Thomas L. McDevitt
IPC分类号： H01L23/498 , G06F11/22 , H01L21/60
CPC分类号： H01L24/11 , H01L23/522 , H01L24/03 , H01L24/05 , H01L24/13 , H01L2224/0401 , H01L2224/05008 , H01L2224/05022 , H01L2224/05096 , H01L2224/05147 , H01L2224/05569 , H01L2224/05571 , H01L2224/13022 , H01L2224/131 , H01L2924/00011 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01073 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2224/05552 , H01L2224/81805
摘要： Disclosed is reinforced via farm interconnect structure for an integrated circuit chip that minimizes delamination caused by tensile stresses applied to the chip through lead-free C4 connections during thermal cycling. The reinforced via farm interconnect structure includes a plurality of vias electrically connecting metal wires within different wiring levels and, for reinforcement, further incorporates dielectric columns into the lower metal wire so that the areas around the metal-to-metal interface between the vias and the lower metal wire contain a relatively strong dielectric-to-dielectric interface. The reinforced via farm interconnect structure can be located in an area of the chip at risk for delamination and, for added strength, can have a reduced via density relative to conventional via farm interconnect structures located elsewhere on the chip. Also disclosed are a method of forming the reinforced via farm interconnect structure and a method of redesigning an integrated circuit chip to include reinforced via farm interconnect structure(s).
摘要翻译： 公开了通过用于集成电路芯片的农场互连结构来加强，其最小化在热循环期间通过无铅C4连接施加到芯片的拉伸应力引起的分层。 增强通孔农场互连结构包括多个通孔，电连接不同布线层内的金属线，并且为了加强，进一步将电介质柱并入下金属线，使得通孔和通孔之间的金属到金属界面周围的区域 下部金属线包含相当强的电介质至电介质界面。 增强的通孔农场互连结构可以位于芯片的具有分层风险的区域中，并且为了增加的强度，可以相对于位于芯片上其他地方的常规通孔农场互连结构，具有降低的通孔密度。 还公开了一种形成加强的通孔农场互连结构的方法和重新设计集成电路芯片以包括增强的农场互连结构的方法。
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公开(公告)号：US20110127673A1
公开(公告)日：2011-06-02
申请号：US12628481
申请日：2009-12-01
IPC分类号： H01L23/532 , H01L21/768
CPC分类号： H01L23/53238 , H01L21/76834 , H01L21/76883 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is an improved integrated circuit wiring structure configured to prevent migration of wiring metal ions (e.g., copper (Cu+) ions in the case of a copper interconnect scheme) onto the surface of an interlayer dielectric material at an interface between the interlayer dielectric material and an insulating cap layer. Specifically, the top surfaces of wires and the top surface of a dielectric layer within which the wires sit are not co-planar. Thus, the interfaces between the wires and an insulating cap layer and between the dielectric layer and the same insulating cap layer are also not co-planar. Such a configuration physically prevents migration of wiring metal ions from the top surface of the wires onto the top surface of the dielectric layer at the interface between the dielectric layer and cap layer and, thereby prevents time dependent dielectric breakdown (TDDB) and eventual device failure. Also disclosed herein are embodiments of a method of a forming such an integrated circuit wiring structure.
摘要翻译： 公开了一种改进的集成电路布线结构，其被配置为防止布线金属离子（例如在铜互连方案的情况下的铜（Cu +）离子）迁移到层间电介质材料的表面上，在层间电介质材料和 绝缘盖层。 具体地，电线的顶表面和电线所在的电介质层的顶表面不是共面的。 因此，电线和绝缘帽层之间以及电介质层和相同绝缘帽层之间的界面也不是共面的。 这种配置物理上防止布线金属离子从电介质顶表面在介电层和盖层之间的界面处迁移到电介质层的顶表面上，从而防止时间依赖的介质击穿（TDDB）和最终的器件故障 。 本文还公开了形成这种集成电路布线结构的方法的实施例。
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公开(公告)号：US20100248479A1
公开(公告)日：2010-09-30
申请号：US12415406
申请日：2009-03-31
IPC分类号： H01L21/304
CPC分类号： H01L21/3212 , C09G1/02
摘要： The instant invention is a method of polishing a substrate including contacting a substrate having at least one metal layer including copper with a chemical-mechanical polishing composition. The CMP composition includes an abrasive, a surfactant, an oxidizer, an organic acid including polyacrylic acid or polymethacrylic acid, a corrosion inhibitor, and a liquid carrier. A portion of the copper in the metal layer is abraded to polish the substrate. A second CMP composition contacts the abraded substrate, the second acrylate free composition including an abrasive, a surfactant, an oxidizer, and a corrosion inhibitor, and a liquid carrier. Any dendrites that may have formed on the substrate are removed through abrasion.
摘要翻译： 本发明是抛光衬底的方法，包括使具有至少一个包含铜的金属层的衬底与化学机械抛光组合物接触。 CMP组合物包括研磨剂，表面活性剂，氧化剂，包括聚丙烯酸或聚甲基丙烯酸的有机酸，腐蚀抑制剂和液体载体。 金属层中的铜的一部分被磨损以抛光基底。 第二CMP组合物接触研磨的基材，第二无丙烯酸酯组合物包含研磨剂，表面活性剂，氧化剂和腐蚀抑制剂以及液体载体。 可能通过磨损去除可能在基底上形成的任何枝晶。
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54.发明申请CURVILINEAR WIRING STRUCTURE TO REDUCE AREAS OF HIGH FIELD DENSITY IN AN INTEGRATED CIRCUIT 有权降低集成电路中高场密度区域的CURVILINEAR接线结构公开(公告)号：US20090288869A1
公开(公告)日：2009-11-26
申请号：US12427775
申请日：2009-04-22
CPC分类号： H01L23/5283 , H01G4/232 , H01G4/306 , H01G4/33 , H01L21/768 , H01L23/5223 , H01L28/86 , H01L28/90 , H01L2924/0002 , Y10T29/49204 , H01L2924/00
摘要： A method for reducing areas of high field density in an integrated circuit is disclosed. In one embodiment, the method includes forming a first curvilinear wiring structure in a first interconnect layer of an integrated circuit. A second curvilinear wiring structure may be formed in a second interconnect layer of the integrated circuit, such that the first and second curvilinear wiring structures are substantially vertically aligned. The first curvilinear wiring structure may then be electrically connected to the second curvilinear wiring structure.
摘要翻译： 公开了一种用于减小集成电路中的高场强的区域的方法。 在一个实施例中，该方法包括在集成电路的第一互连层中形成第一曲线布线结构。 可以在集成电路的第二互连层中形成第二曲线布线结构，使得第一和第二曲线布线结构基本上垂直对齐。 然后可以将第一曲线性布线结构电连接到第二曲线布线结构。
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公开(公告)号：US20080146040A1
公开(公告)日：2008-06-19
申请号：US12041782
申请日：2008-03-04
IPC分类号： H01L21/31
CPC分类号： C23C16/04 , C23C16/513 , H01J37/32366
摘要： A method and an apparatus for performing the method. The method includes: (a) providing an apparatus, wherein the apparatus comprises (i) a chamber, (ii) a plasma device being in and coupled to the chamber, (iii) a shower head being in and coupled to the chamber, and (iv) a chuck being in and coupled to the chamber; (b) placing the substrate on the chuck; (c) using the plasma device to receive a plasma device gas and generate a plasma; (d) directing the plasma at a pre-specified area on the substrate; and (e) using the shower head to receive and distribute a shower head gas in the chamber, wherein the plasma device gas and the shower head gas are selected such that the plasma and the shower head gas when mixed with each other result in a chemical reaction that forms a film at the pre-specified area on the substrate.
摘要翻译： 一种用于执行该方法的方法和装置。 该方法包括：（a）提供一种设备，其中所述设备包括（i）室，（ii）位于室中并耦合到所述室的等离子体设备，（iii）淋浴喷头位于并联接到所述室，以及 （iv）卡盘位于并联接到所述腔室; （b）将基板放置在卡盘上; （c）使用等离子体装置接收等离子体装置气体并产生等离子体; （d）将等离子体引导到基板上的预定区域; 以及（e）使用所述淋浴头来接收和分配所述腔室中的淋浴头气体，其中所述等离子体装置气体和所述喷淋头气体被选择为使得当彼此混合时所述等离子体和所述淋浴头气体产生化学物质 在基板上的预定区域形成膜的反应。
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公开(公告)号：US06991971B2
公开(公告)日：2006-01-31
申请号：US10675177
申请日：2003-09-30
IPC分类号： H01L21/82
CPC分类号： H01L23/53295 , H01L23/5256 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating a fuse for a semiconductor device. The method including: providing a substrate; forming a first dielectric layer on a top surface of said substrate; forming a dielectric mandrel on a top surface of said first dielectric layer; forming a second dielectric layer on top of said mandrel and a top surface of said first dielectric layer forming contact openings down to said substrate in said first and second dielectric layers on opposite sides of said mandrel, said contacts spaced away from said mandrel and leaving portions of said second dielectric layer between said mandrel and said contacts; removing said second dielectric layer from over said mandrel between said contact openings to form a trough; and filling said trough and contact openings with a conductor.
摘要翻译： 一种制造用于半导体器件的熔丝的方法。 该方法包括：提供衬底; 在所述衬底的顶表面上形成第一电介质层; 在所述第一介电层的顶表面上形成介电心轴; 在所述心轴的顶部上形成第二电介质层，并且所述第一电介质层的顶表面在所述心轴的相对侧上的所述第一和第二介电层中向下形成接触开口，所述触头与所述心轴间隔开并留下部分 所述第二电介质层位于所述心轴和所述触头之间; 从所述心轴上的所述接触开口之间移除所述第二电介质层以形成槽; 并用导体填充所述槽和接触开口。
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公开(公告)号：US06946379B2
公开(公告)日：2005-09-20
申请号：US10860470
申请日：2004-06-03
IPC分类号： H01L23/525 , H01L23/544 , H01L21/44
CPC分类号： H01L23/544 , H01L23/5258 , H01L2223/54426 , H01L2223/54453 , H01L2223/5446 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having at least one fuse and an alignment mark formed therein. An etch resistant layer over the surface of the fuse and alignment mark, which provides a uniform passivation thickness for use in conjunction with laser fuse deletion processes.
摘要翻译： 一种具有形成在其中的至少一个熔丝和对准标记的半导体器件。 在熔断器和对准标记的表面上的抗蚀刻层，其提供与激光熔丝删除工艺结合使用的均匀的钝化厚度。
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公开(公告)号：US06667533B2
公开(公告)日：2003-12-23
申请号：US09684000
申请日：2002-03-11
IPC分类号： H01L2900
CPC分类号： H01L23/53295 , H01L23/5256 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a conductive fuse for a semiconductor device, comprising: a pair of contact portions integrally connected to a fusible portion by connecting portions; the contact portions thicker than the connecting portions and the connecting portions thicker than the fusible portion; a first dielectric under the connecting portions and the fusible portion and extending between the pair of contact portions; and a second dielectric between the first dielectric and the fusible portion, the second dielectric extending between the connecting portions and defining the length of the fusible portion.
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公开(公告)号：US06518643B2
公开(公告)日：2003-02-11
申请号：US09816278
申请日：2001-03-23
IPC分类号： H01L2900
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： A substrate having at least one fuse in a fuse layer. An upper etch-stop layer over the fuse, a lower etch-stop layer having a different etch-chemistry over the fuse and, optionally, a diffusion barrier layer immediately over the fuse. The lower etch-stop later and the optional diffusion barrier providing a uniform passivation thickness for use in conjunction with laser fuse deletion processes. An upper etch-resistant layer over the lower etch-resistant layer and having an etch chemistry selective to that of the lower etch-resistant layer. Methods for providing a uniform passivation thickness over all the fuses, and for deleting such fuses.
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60.发明授权Method of depositing conductors in high aspect ratio apertures using a collimator 失效使用准直器在高纵横比孔中沉积导体的方法
公开(公告)号：US5401675A
公开(公告)日：1995-03-28
申请号：US36224
申请日：1993-03-24
申请人： Pei-Ing P. Lee , Thomas J. Licata , Thomas L. McDevitt , Paul C. Parries , Scott L. Pennington , James G. Ryan , David C. Strippe
发明人： Pei-Ing P. Lee , Thomas J. Licata , Thomas L. McDevitt , Paul C. Parries , Scott L. Pennington , James G. Ryan , David C. Strippe
IPC分类号： C23C14/46 , C23C14/04 , H01L21/203 , H01L21/28 , H01L21/285 , H01L21/768 , H05K3/40 , H01L21/441
CPC分类号： C23C14/044 , H01L21/76877 , H05K3/4076
摘要： A process for sputter deposition wherein high aspect ratio apertures are coated with conductive films exhibiting low bulk resistivity, low impurity concentrations, and regular morphologies. A collimator is used having an aspect ratio that approximates the aspect ratio of the apertures.
摘要翻译： 用于溅射沉积的方法，其中高纵横比孔被涂覆有表现出低体积电阻率，低杂质浓度和规则形态的导电膜。 使用具有近似于孔的纵横比的纵横比的准直器。
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