公开(公告)号：US20060274578A1

公开(公告)日：2006-12-07

申请号：US11443205

申请日：2006-05-31

申请人： Pan-Suk Kwak ,  Dae-Seok Byeon

发明人： Pan-Suk Kwak ,  Dae-Seok Byeon

IPC分类号： G11C16/04

CPC分类号： G11C16/24 ,  G11C16/0483 ,  G11C16/16

摘要： A NAND flash memory device comprises a memory cell array comprising a plurality of memory cells, a plurality of page buffers, and an isolation circuit connected between the memory cell array and the plurality of page buffers. The isolation circuit comprises a high voltage transistor adapted to disconnect a first bit line connected to the memory cell array from a second bit line connected to the one of the page buffers during an erase operation of the NAND flash memory device. During the read operation, a third bit line arranged in parallel with the second bit line and connected to one of the page buffers is discharged to prevent the page buffer from being damaged due to coupling capacitance between the second and third bit lines.

摘要翻译： NAND闪速存储器件包括存储单元阵列，该存储单元阵列包括多个存储单元，多个页缓冲器以及连接在存储单元阵列与多个页缓冲器之间的隔离电路。 隔离电路包括高电压晶体管，其适于在NAND闪速存储器件的擦除操作期间将连接到存储单元阵列的第一位线与连接到该页缓冲器之一的第二位线断开。 在读取操作期间，放电与第二位线并联并连接到页面缓冲器之一的第三位线，以防止页缓冲器由于第二位线和第三位线之间的耦合电容而损坏。

公开(公告)号：US20060092703A1

公开(公告)日：2006-05-04

申请号：US11205245

申请日：2005-08-16

申请人： Dong-Hyuk Chae ,  Dae-Seok Byeon

发明人： Dong-Hyuk Chae ,  Dae-Seok Byeon

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C16/0483 ,  G11C16/08

摘要： Flash memory devices include a memory array having a plurality of NAND strings of EEPROM cells therein. A word line driver is provided to improve programming efficiency. The word line driver is electrically coupled to the memory array by a plurality of word lines. The word line driver includes a plurality of pass voltage switches. These switches have outputs electrically coupled by diodes to the plurality of word lines. Methods of programming flash memory devices include applying a pass voltage to a plurality of unselected word lines in a non-volatile memory array while simultaneously applying a sequentially ramped program voltage to a selected word line in the non-volatile memory array. The sequentially ramped program voltage has a minimum value that is clamped by a word line driver to a level not less than a value of the pass voltage.

摘要翻译： 闪存器件包括其中具有多个EEPROM串的NAND串的存储器阵列。 提供字线驱动程序以提高编程效率。 字线驱动器通过多个字线电耦合到存储器阵列。 字线驱动器包括多个通过电压开关。 这些开关具有由二极管电耦合到多个字线的输出。 编程闪速存储器件的方法包括在非易失性存储器阵列中向多个未选择的字线施加通过电压，同时将顺序斜坡的编程电压施加到非易失性存储器阵列中的选定字线。 顺序斜坡编程电压具有被字线驱动器钳位到不小于通过电压值的电平的最小值。

公开(公告)号：US07038949B2

公开(公告)日：2006-05-02

申请号：US10957307

申请日：2004-09-30

申请人： Dong-Hyuk Chae ,  Dae-Seok Byeon

发明人： Dong-Hyuk Chae ,  Dae-Seok Byeon

IPC分类号： G11C16/06

CPC分类号： G11C16/12 ,  G11C16/3454 ,  G11C16/3459

摘要： A non-volatile memory device includes a word line voltage generator circuit for generating a word line voltage to be supplied to a selected row in response to step control signals and a program controller for sequentially activating the step control signals during a program cycle. During the program cycle, the word line voltage generator circuit controls the increment of the word line voltage differently according to the mode of operation, namely, a test mode or a normal mode. Thus test time can be shortened.

摘要翻译： 非易失性存储器件包括字线电压发生器电路，用于响应于步进控制信号产生要提供给选定行的字线电压;以及程序控制器，用于在编程周期期间顺序激活步进控制信号。 在编程周期中，字线电压发生器电路根据操作模式，即测试模式或正常模式，不同地控制字线电压的增量。 因此可以缩短测试时间。

公开(公告)号：US06888756B2

公开(公告)日：2005-05-03

申请号：US10376615

申请日：2003-02-28

申请人： Dae-Seok Byeon ,  June Lee ,  Gyung-Han Lee

发明人： Dae-Seok Byeon ,  June Lee ,  Gyung-Han Lee

IPC分类号： G11C16/06 ,  G11C5/14 ,  G11C16/02 ,  G11C16/24 ,  G11C16/30 ,  G11C16/04

CPC分类号： G11C5/147 ,  G11C16/24 ,  G11C16/30

摘要： The disclosure is a non-volatile semiconductor memory device including a bias circuit that generates a bias voltage for controlling an NMOS transistor connected to both a bit line and a page buffer circuit. The bias circuit generates a first voltage, which is greater than a power source voltage, as the bias signal in a precharge period of a read operation. The bias circuit also generates a second voltage, which is less than the power source voltage, as the bias signal in a sensing period of the read operation.

摘要翻译： 本公开是一种非易失性半导体存储器件，包括偏置电路，该偏置电路产生用于控制连接到位线和页缓冲器电路的NMOS晶体管的偏置电压。 偏置电路在读取操作的预充电时段中产生大于电源电压的第一电压作为偏置信号。 偏置电路还在读取操作的感测周期中产生小于电源电压的第二电压作为偏置信号。

公开(公告)号：US09851912B2

公开(公告)日：2017-12-26

申请号：US15443647

申请日：2017-02-27

申请人： Sang-Wan Nam ,  Doo-Hyun Kim ,  Dae-Seok Byeon ,  Chi-Weon Yoon

发明人： Sang-Wan Nam ,  Doo-Hyun Kim ,  Dae-Seok Byeon ,  Chi-Weon Yoon

IPC分类号： G11C11/34 ,  G11C16/04 ,  G06F3/06

CPC分类号： G06F3/0619 ,  G06F3/061 ,  G06F3/0644 ,  G06F3/0655 ,  G06F3/0688 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/16 ,  G11C16/26 ,  G11C16/34 ,  G11C16/3459 ,  H01L27/11582

摘要： A memory device is provided as follows. A memory cell region includes a plurality of blocks, each block including a plurality of NAND strings. A control logic divides the plurality of blocks into a plurality of block regions based on a smaller distance of a first distance with respect to a first edge of the memory cell region and a second distance with respect to a second edge of the memory cell region and controls an operation performed on the memory cell region using a plurality of bias sets of operation parameters for the operation. Each bias set is associated with one of the block regions.

公开(公告)号：US08461627B2

公开(公告)日：2013-06-11

申请号：US12635769

申请日：2009-12-11

申请人： Dae-Seok Byeon

发明人： Dae-Seok Byeon

IPC分类号： H01L27/088

CPC分类号： H01L27/11519 ,  H01L27/105 ,  H01L27/11551 ,  H01L27/11565 ,  H01L27/11578

摘要： In a stack array structure for a semiconductor memory device, a first semiconductor layer includes a plurality of first cell strings, and a second semiconductor including a plurality of second cell strings. Bit-line contact plugs are configured to couple a bit-line to two adjacent first cell strings aligned in series in a bit-line direction, and to further couple the bit-line to two adjacent second cell strings respectively located over the two adjacent first cell strings. Common source line contact plugs are configured to couple a common source line to the two adjacent first cell strings and the two adjacent second cell strings. Pocket p-well contact plugs are located at positions corresponding to a layout of the bit-line plugs and/or common source line plugs, and are configured to couple a pocket p-well line to the first semiconductor layer and the second semiconductor layer.

摘要翻译： 在半导体存储器件的堆叠阵列结构中，第一半导体层包括多个第一单元串，以及包括多个第二单元串的第二半导体。 位线接触插头被配置为将位线耦合到在位线方向上串联对准的两个相邻的第一单元串，并且还将位线耦合到分别位于两个相邻的第一单元上的两个相邻的第二单元串 单元格串。 公共源线接触插头被配置为将公共源极线耦合到两个相邻的第一单元串和两个相邻的第二单元串。 口袋p阱接触插头位于对应于位线插头和/或公共源极线插头的布局的位置处，并且被配置为将口袋p阱线耦合到第一半导体层和第二半导体层。

公开(公告)号：US20100302869A1

公开(公告)日：2010-12-02

申请号：US12854987

申请日：2010-08-12

申请人： Dae-Seok Byeon

发明人： Dae-Seok Byeon

IPC分类号： G11C16/06 ,  G11C16/04

CPC分类号： G11C16/30 ,  G11C16/24

摘要： A method of operating a flash memory device includes a first operating mode and a second operating mode having different operating speeds. Each one of the first and second operating modes includes a bit line set-up interval and at least one additional interval. The flash memory is divided into first and second mats connected to respective first and second R/W circuits. During the bit line set-up interval of the second operating mode, the flash memory controls operation of both the first and second R/W circuits in a time division approach to stagger respective peak current intervals for the first and second mats.

摘要翻译： 操作闪速存储器件的方法包括具有不同操作速度的第一操作模式和第二操作模式。 第一和第二操作模式中的每一个包括位线建立间隔和至少一个附加间隔。 闪存被分成连接到相应的第一和第二R / W电路的第一和第二垫。 在第二操作模式的位线设置间隔期间，闪速存储器以时分方式控制第一和第二R / W电路的操作，以交错第一和第二垫的相应的峰值电流间隔。

公开(公告)号：US07800971B2

公开(公告)日：2010-09-21

申请号：US12541429

申请日：2009-08-14

申请人： Jin-Sung Park ,  Dae-Seok Byeon

发明人： Jin-Sung Park ,  Dae-Seok Byeon

IPC分类号： G11C7/00 ,  G11C11/34 ,  G11C16/04

CPC分类号： G11C16/10 ,  G11C2216/14

摘要： A flash memory device is programmed by loading first data into a page buffer of a first mat. Second data is loaded into a page buffer of a second mat while programming the first data in a first memory block of the first mat.

摘要翻译： 通过将第一数据加载到第一垫的页缓冲器中来编程闪存器件。 第二数据被加载到第二垫的页缓冲器中，同时在第一垫的第一存储块中编程第一数据。

公开(公告)号：US07768831B2

公开(公告)日：2010-08-03

申请号：US12109466

申请日：2008-04-25

申请人： Dae-Seok Byeon ,  Young-Ho Lim

发明人： Dae-Seok Byeon ,  Young-Ho Lim

IPC分类号： G11C16/06

CPC分类号： G11C16/10 ,  G11C8/10 ,  G11C8/12 ,  G11C29/806 ,  G11C29/844

摘要： A flash memory device includes multiple memory blocks, a decoder configured to select at least one of the memory blocks in response to block select signals, and a controller configured to generate the block select signals in response to a block address. When the block address corresponds to a bad block, the controller generates the block select signals to cause the decoder to interrupt selection of a memory block corresponding to the block address.

摘要翻译： 闪存器件包括多个存储器块，被配置为响应于块选择信号来选择至少一个存储器块的解码器，以及被配置为响应于块地址产生块选择信号的控制器。 当块地址对应于坏块时，控制器产生块选择信号以使解码器中断对应于块地址的存储块的选择。

公开(公告)号：US07692967B2

公开(公告)日：2010-04-06

申请号：US11776729

申请日：2007-07-12

申请人： Dae-Seok Byeon ,  Young-ho Lim

发明人： Dae-Seok Byeon ,  Young-ho Lim

IPC分类号： G11C11/34

CPC分类号： G11C16/3418 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/30 ,  G11C16/3427

摘要： A method of programming a nonvolatile memory device using hybrid local boosting which includes a plurality of cell strings each having a plurality of electrically erasable and programmable memory cells connected in series and a plurality of wordlines respectively connected to control gates of the plurality of memory cells. The address of a selected cell that is to be programmed is received. A determination is made as to whether a selected wordline connected to the selected cell is located above or under a reference wordline based on the received address. The selected cell is programmed using local boosting when the selected wordline corresponds to the reference wordline or is located above the reference wordline. The selected cell is programmed using self-boosting when the selected wordline is located under the reference wordline. The programming method reduces circuit size of a nonvolatile memory device employing the programming method and efficiently prevents program disturbance due to charge sharing.

摘要翻译： 一种使用混合局部升压来编程非易失性存储器件的方法，该方法包括多个单元串，每个单元串具有分别连接到多个存储器单元的控制栅极的多个电可擦除可编程存储器单元和多个字线。 接收要编程的所选单元的地址。 确定连接到所选择的单元的所选择的字线是否位于参考字线的上方或下方，基于所接收的地址。 当所选择的字线对应于参考字线或位于参考字线上方时，使用本地升压来编程所选单元格。 当所选择的字线位于参考字线下方时，使用自增强来对所选择的单元进行编程。 编程方法减少了使用编程方法的非易失性存储器件的电路尺寸，并且有效地防止了由于电荷共享引起的程序干扰。