公开(公告)号：US20060237785A1

公开(公告)日：2006-10-26

申请号：US11112820

申请日：2005-04-22

申请人： Meikei Ieong ,  Qiqing Ouyang ,  Kern Rim

发明人： Meikei Ieong ,  Qiqing Ouyang ,  Kern Rim

IPC分类号： H01L29/76

CPC分类号： H01L21/823807 ,  H01L27/0922 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

摘要： The present invention provides CMOS structures including at least one strained pFET that is located on a rotated semiconductor substrate to improve the device performance. Specifically, the present invention utilizes a Si-containing semiconductor substrate having a (100) crystal orientation in which the substrate is rotated by about 45° such that the CMOS device channels are located along the direction. Strain can be induced upon the CMOS structure including at least a pFET and optionally an nFET, particularly the channels, by forming a stressed liner about the FET, by forming embedded stressed wells in the substrate, or by utilizing a combination of embedded stressed wells and a stressed liner. The present invention also provides methods for fabricating the aforesaid semiconductor structures.

摘要翻译： 本发明提供CMOS结构，其包括位于旋转的半导体衬底上的至少一个应变pFET，以改善器件性能。 具体地，本发明利用具有（100）晶体取向的含Si半导体衬底，其中衬底旋转约45°，使得CMOS器件沟道沿<100>方向定位。 通过在衬底中形成嵌入的应力阱，或者通过利用嵌入的应力阱的组合，或者通过利用嵌入的应力阱的组合，可以在包括至少pFET和任选的nFET，特别是沟道的CMOS结构上诱导应变， 一个紧张的班轮。 本发明还提供了制造上述半导体结构的方法。

公开(公告)号：US20060211184A1

公开(公告)日：2006-09-21

申请号：US11436756

申请日：2006-05-18

申请人： Diane Boyd ,  Bruce Doris ,  Meikei Ieong ,  Devendra Sadana

发明人： Diane Boyd ,  Bruce Doris ,  Meikei Ieong ,  Devendra Sadana

IPC分类号： H01L21/84

CPC分类号： H01L29/78696 ,  H01L29/66545 ,  H01L29/66772 ,  H01L29/78609 ,  H01L29/78684

摘要： The present invention provides a thin channel MOSFET having low external resistance. In broad terms, a silicon-on-insulator structure comprising a SOI layer located atop a buried insulating layer, said SOI layer having a channel region which is thinned by the presence of an underlying localized oxide region that is located on top of and in contact with said buried insulating layer; and a gate region located atop said SOI layer, wherein said localized oxide region is self-aligned with the gate region. A method for forming the inventive MOSFET is also provided comprising forming a dummy gate region atop a substrate; implanting oxide forming dopant through said dummy gate to create a localized oxide region in a portion of the substrate aligned to the dummy gate region that thins a channel region; forming source/drain extension regions abutting said channel region; and replacing the dummy gate with a gate conductor.

摘要翻译： 本发明提供一种具有低外部电阻的薄沟道MOSFET。 广义而言，包括位于掩埋绝缘层顶部的SOI层的绝缘体上硅结构，所述SOI层具有沟槽区，该沟道区被存在位于并接触之下的下面的局部氧化物区域 与所述掩埋绝缘层; 以及位于所述SOI层上方的栅极区域，其中所述局部氧化物区域与栅极区域自对准。 还提供了一种用于形成本发明的MOSFET的方法，包括在衬底顶部形成虚拟栅极区; 通过所述伪栅极注入形成氧化物的掺杂剂，以在与沟道区域的伪栅极区对准的衬底的一部分中产生局部氧化物区域; 形成邻接所述沟道区的源/漏扩展区; 并用栅极导体代替虚拟栅极。

公开(公告)号：US07098508B2

公开(公告)日：2006-08-29

申请号：US10932982

申请日：2004-09-02

申请人： Meikei Ieong ,  Min Yang

发明人： Meikei Ieong ,  Min Yang

IPC分类号： H01L29/72

CPC分类号： H01L29/66772 ,  H01L21/76264 ,  H01L21/76278 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/1054 ,  H01L29/78654 ,  H01L29/78684

摘要： The invention provides integrated semiconductor devices that are formed upon an SOI substrate having different crystal orientations that provide optimal performance for a specific device. Specifically, an integrated semiconductor structure including at least an SOI substrate having a top semiconductor layer of a first crystallographic orientation and a semiconductor material of a second crystallographic orientation, wherein the semiconductor material is substantially coplanar and of substantially the same thickness as that of the top semiconductor layer and the first crystallographic orientation is different from the second crystallographic orientation is provided. The SOI substrate is formed by forming an opening into a structure that includes at least a first semiconductor layer and a second semiconductor layer that have different crystal orientations. The opening extends to the first semiconductor layer. A semiconductor material is epitaxial grown in the opening and then various etching and etch back processing steps are used in forming the SOI substrate.

摘要翻译： 本发明提供了在具有不同晶体取向的SOI衬底上形成的集成半导体器件，其为特定器件提供最佳性能。 具体地说，一种集成半导体结构，其至少包括具有第一晶体取向的顶部半导体层和第二晶体取向的半导体材料的SOI衬底，其中半导体材料基本上是共面的，并且具有与顶部基本相同的厚度 半导体层和第一晶体取向与第二晶体取向不同。 通过将开口形成为至少包括具有不同晶体取向的第一半导体层和第二半导体层的结构，形成SOI衬底。 开口延伸到第一半导体层。 半导体材料在开口中外延生长，然后在形成SOI衬底中使用各种蚀刻和回蚀加工步骤。

公开(公告)号：US07094634B2

公开(公告)日：2006-08-22

申请号：US10710277

申请日：2004-06-30

申请人： Huilong Zhu ,  Bruce B. Doris ,  Meikei Ieong ,  Phillip J. Oldiges ,  Min Yang

发明人： Huilong Zhu ,  Bruce B. Doris ,  Meikei Ieong ,  Phillip J. Oldiges ,  Min Yang

IPC分类号： H01L21/84 ,  H01L21/00

CPC分类号： H01L21/76254 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02639 ,  H01L21/84 ,  H01L29/045 ,  H01L29/785 ,  Y10T428/249921 ,  Y10T428/249922

摘要： The present invention provides a method of forming a substantially planar SOI substrate having multiple crystallographic orientations including the steps of providing a multiple orientation surface atop a single orientation layer, the multiple orientation surface comprising a first device region contacting and having a same crystal orientation as the single orientation layer, and a second device region separated from the first device region and the single orientation layer by an insulating material, wherein the first device region and the second device region have different crystal orientations; producing a damaged interface in the single orientation layer; bonding a wafer to the multiple orientation surface; separating the single orientation layer at the damaged interface; wherein a damaged surface of said single orientation layer remains; and planarizing the damaged surface until a surface of the first device region is substantially coplanar to a surface of the second device region.

公开(公告)号：US07041538B2

公开(公告)日：2006-05-09

申请号：US10713971

申请日：2003-11-14

申请人： Meikei Ieong ,  Omer H. Dokumaci ,  Thomas S. Kanarsky ,  Victor Ku

发明人： Meikei Ieong ,  Omer H. Dokumaci ,  Thomas S. Kanarsky ,  Victor Ku

IPC分类号： H01L21/00

CPC分类号： H01L29/78696 ,  H01L29/456 ,  H01L29/4908 ,  H01L29/66545 ,  H01L29/66772 ,  H01L29/78618 ,  H01L29/78621

摘要： A high-performance recessed channel CMOS device including an SOI layer having a recessed channel region and adjoining extension implant regions and optional halo implant regions; and at least one gate region present atop the SOI layer and a method for fabricating the same are provided. The adjoining extension and optional halo implant regions have an abrupt lateral profile and are located beneath said gate region.

摘要翻译： 一种高性能凹陷沟道CMOS器件，包括具有凹陷沟道区域和相邻的延伸注入区域和可选的晕轮植入区域的SOI层; 并且提供存在于SOI层顶上的至少一个栅极区域及其制造方法。 邻接的延伸部分和可选的晕轮植入区域具有突然的侧向轮廓并且位于所述栅极区域下方。

公开(公告)号：US20060001095A1

公开(公告)日：2006-01-05

申请号：US10710273

申请日：2004-06-30

申请人： Bruce Doris ,  Meikei Ieong ,  Zhibin Ren ,  Paul Solomon ,  Min Yang

发明人： Bruce Doris ,  Meikei Ieong ,  Zhibin Ren ,  Paul Solomon ,  Min Yang

IPC分类号： H01L29/76 ,  H01L21/00

CPC分类号： H01L29/78696 ,  H01L29/66545 ,  H01L29/66772

摘要： A method of creating ultra tin body fully-depleted SOI MOSFETs in which the SOI thickness changes with gate-length variations thereby minimizing the threshold voltage variations that are typically caused by SOI thickness and gate-length variations is provided. The method of present invention uses a replacement gate process in which nitrogen is implanted to selectively retard oxidation during formation of a recessed channel. A self-limited chemical oxide removal (COR) processing step can be used to improve the control in the recessed channel step. If the channel is doped, the inventive method is designed such that the thickness of the SOI layer is increased with shorter channel length. If the channel is undoped or counter-doped, the inventive method is designed such that the thickness of the SOI layer is decreased with shorter channel length.

摘要翻译： 提供了一种制造超薄体全耗尽SOI SOI的方法，其中SOI厚度随着栅极长度变化而变化，从而最小化通常由SOI厚度和栅极长度变化引起的阈值电压变化。 本发明的方法使用其中注入氮的替代浇口工艺，以便在形成凹陷通道期间选择性地延迟氧化。 可以使用自限制化学氧化物去除（COR）处理步骤来改善凹陷通道步骤中的控制。 如果沟道被掺杂，则本发明的方法被设计成使得SOI层的厚度随着沟道长度的增加而增加。 如果通道是未掺杂或反掺杂的，则本发明的方法被设计成使得SOI层的厚度随着沟道长度的减小而减小。

公开(公告)号：US20050263797A1

公开(公告)日：2005-12-01

申请号：US11146624

申请日：2005-06-07

申请人： Kevin Chan ,  Guy Cohen ,  Meikei Ieong ,  Ronnen Roy ,  Paul Solomon ,  Min Yang

发明人： Kevin Chan ,  Guy Cohen ,  Meikei Ieong ,  Ronnen Roy ,  Paul Solomon ,  Min Yang

IPC分类号： H01L29/417 ,  H01L21/02 ,  H01L21/265 ,  H01L21/336 ,  H01L21/76 ,  H01L21/762 ,  H01L27/12 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786 ,  H01L21/4763 ,  H01L21/8234 ,  H01L27/148 ,  H01L29/76 ,  H01L29/768 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/66484 ,  H01L21/26533 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/7831 ,  H01L29/7834 ,  H01L29/78648

摘要： A double-gate field effect transistor (DGFET) structure and method of forming such a structure in which the parasitic capacitance under the source/drain regions is substantially reduced are provided. Two new means to reduce the parasitic capacitance under the source/drain regions are provided. Firstly, the silicon area outside the gate is converted to oxide while protecting a silicon ledge adjacent to the gate with a first spacer. The oxidation can be facilitated using a self-aligned oxygen implant, or implant of some other species. Secondly, the first spacer is removed, replaced with a second spacer, and a new silicon source/drain area is grown by employing lateral selective epi overgrowth and using the now exposed silicon ledge as a seed, over the self-aligned oxide isolation region. This achieves a low-capacitance to the back-plane, while retaining control of the threshold voltages.

摘要翻译： 提供了双栅场效应晶体管（DGFET）结构和形成这样的结构的方法，其中源/漏区下的寄生电容大大减小。 提供了两种降低源极/漏极区下寄生电容的新手段。 首先，栅极外部的硅区域被转换为氧化物，同时用第一间隔物保护邻近栅极的硅凸缘。 使用自对准氧植入物或某些其它物种的植入物可以促进氧化。 其次，去除第一间隔物，用第二间隔物代替，通过采用横向选择性外延生长并使用现在暴露的硅壁缘作为种子，在自对准氧化物隔离区域上生长新的硅源/漏区。 这实现了对背板的低电容，同时保持阈值电压的控制。

公开(公告)号：US20050221543A1

公开(公告)日：2005-10-06

申请号：US11125063

申请日：2005-05-09

申请人： Andres Bryant ,  Meikei Ieong ,  K. Muller ,  Edward Nowak ,  David Fried ,  Jed Rankin

发明人： Andres Bryant ,  Meikei Ieong ,  K. Muller ,  Edward Nowak ,  David Fried ,  Jed Rankin

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786 ,  H01L21/00

CPC分类号： H01L29/4908 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/66795 ,  H01L29/785

摘要： Accordingly, the present invention provides a double gated transistor and a method for forming the same that results in improved device performance and density. The preferred embodiment of the present invention uses provides a double gated transistor with asymmetric gate doping, where one of the double gates is doped degenerately n-type and the other degenerately p-type. By doping on of the gates n-type, and the other p-type, the threshold voltage of the resulting device is improved. In particular, by asymmetrically doping the two gates, the resulting transistor can, with adequate doping of the body, have a threshold voltage in a range that enables low-voltage CMOS operation. For example, a transistor can be created that has a threshold voltage between 0V and 0.5V for nFETs and between 0 and −0.5V for pFETs.

摘要翻译： 因此，本发明提供一种双门控晶体管及其形成方法，其导致改进的器件性能和密度。 本发明的优选实施例提供了具有不对称栅极掺杂的双门控晶体管，其中双栅极中的一个被简并掺杂为n型，另一个为简并p型。 通过掺杂栅极n型和另一种p型，所得器件的阈值电压得到改善。 特别地，通过不对称地掺杂两个栅极，所得到的晶体管可以通过适当掺杂的体，在允许低电压CMOS操作的范围内具有阈值电压。 例如，可以产生对于nFET具有在0V和0.5V之间的阈值电压并且对于pFET而言在0和-0.5V之间的晶体管。

公开(公告)号：US20050127362A1

公开(公告)日：2005-06-16

申请号：US10732322

申请日：2003-12-10

申请人： Ying Zhang ,  Bruce Doris ,  Thomas Kanarsky ,  Meikei Ieong ,  Jakub Kedzierski

发明人： Ying Zhang ,  Bruce Doris ,  Thomas Kanarsky ,  Meikei Ieong ,  Jakub Kedzierski

IPC分类号： H01L29/812 ,  H01L21/335 ,  H01L21/336 ,  H01L21/338 ,  H01L29/423 ,  H01L29/786 ,  H01L29/76

CPC分类号： H01L29/785 ,  H01L29/42384 ,  H01L29/66795

摘要： A field effect device is disclosed which has a body formed of a crystalline semiconductor material and has at least one vertically oriented section and at least one horizontally oriented section. The device is produced in SOI technology by fabricating first a formation of the device in masking insulators, and then transferring this formation through several etching steps into the SOI layer. The segmented field effect device combines FinFET, or fully depleted silicon-on-insulator FETs, type devices with fully depleted planar devices. This combination allows device width control with FinFET type devices. The segmented field effect device gives high current drive for a given layout area. The segmented field effect devices allow for the fabrication of high performance processors.

摘要翻译： 公开了一种场效应器件，其具有由晶体半导体材料形成的主体，并具有至少一个垂直取向部分和至少一个水平定向部分。 该器件通过在掩模绝缘体中首先制造器件的形成，然后将该形成通过几个蚀刻步骤转移到SOI层中而以SOI技术制造。 分段场效应器件结合FinFET或完全耗尽的绝缘体上硅FET，具有完全耗尽的平面器件的类型器件。 该组合允许使用FinFET类型器件进行器件宽度控制。 分段场效应器件为给定的布局区域提供高电流驱动。 分段场效应器件允许制造高性能处理器。

公开(公告)号：US20050118826A1

公开(公告)日：2005-06-02

申请号：US10725848

申请日：2003-12-02

申请人： Diane Boyd ,  Bruce Doris ,  Meikei Ieong ,  Devendra Sadana

发明人： Diane Boyd ,  Bruce Doris ,  Meikei Ieong ,  Devendra Sadana

IPC分类号： H01L21/265 ,  H01L21/28 ,  H01L21/311 ,  H01L21/336 ,  H01L29/10 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78

CPC分类号： H01L21/28194 ,  H01L21/26533 ,  H01L21/28202 ,  H01L29/1083 ,  H01L29/49 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/78

摘要： The present invention comprises a method for forming an ultra-thin channel MOSFET and the ultra-thin channel MOSFET produced therefrom. Specifically, the method comprises providing an SOI substrate having a buried insulating layer underlying an SOI layer; forming a pad stack atop the SOI layer; forming a block mask having a channel via atop the pad stack; providing a localized oxide region in the SOI layer on top of the buried insulating layer thereby thinning a portion of the SOI layer, the localized oxide region being self-aligned with the channel via; forming a gate in the channel via; removing at least the block mask; and forming source/drain extensions in the SOI layer abutting the thinned portion of the SOI layer. Providing the localized oxide region further comprises implanting oxygen dopant through the channel via into a portion of the SOI layer; and annealing the dopant to create the localized oxide region.

摘要翻译： 本发明包括用于形成超薄沟道MOSFET的方法和由其制造的超薄沟道MOSFET。 具体地说，该方法包括：在SOI层的下方提供具有掩埋绝缘层的SOI衬底; 在SOI层顶上形成焊盘堆叠; 通过所述垫堆叠的顶部形成具有通道的块掩模; 在所述掩埋绝缘层的顶部上的所述SOI层中提供局部氧化物区域，从而使所述SOI层的一部分变薄，所述局部氧化物区域与所述沟道通孔自对准; 在通道通道中形成一个门; 至少去除阻挡掩模; 以及在与SOI层的薄化部分邻接的SOI层中形成源极/漏极延伸部。 提供局部氧化物区域还包括通过沟道通孔将氧掺杂剂注入到SOI层的一部分中; 并退火掺杂剂以产生局部氧化物区域。