公开(公告)号：US20220352113A1

公开(公告)日：2022-11-03

申请号：US17868946

申请日：2022-07-20

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsin-Chieh Yao ,  Chung-Ju Lee ,  Chih Wei Lu ,  Hsi-Wen Tien ,  Yu-Teng Dai ,  Wei-Hao Liao

IPC分类号： H01L23/00 ,  H01L21/768

摘要： The present disclosure relates to a semiconductor structure including an interconnect structure disposed over a semiconductor substrate. A lower metal line is disposed at a first height over the semiconductor substrate and extends through a first interlayer dielectric layer. A second interlayer dielectric layer is disposed at a second height over the semiconductor substrate and comprises a first dielectric material. An upper metal line is disposed at a third height over the semiconductor substrate. A via is disposed at the second height. The via extends between the lower metal line and the upper metal line. A protective dielectric structure is disposed at the second height. The protective dielectric structure comprises a protective dielectric material and is disposed along a first set of opposing sidewalls of the via, the protective dielectric material differing from the first dielectric material.

公开(公告)号：US20220302025A1

公开(公告)日：2022-09-22

申请号：US17834204

申请日：2022-06-07

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Teng Dai ,  Chung-Ju Lee ,  Chih Wei Lu ,  Hsin-Chieh Yao ,  Hsi-Wen Tien ,  Wei-Hao Liao

IPC分类号： H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L23/528

摘要： Some embodiments relate to a method for forming a semiconductor structure, the method includes forming a first dielectric layer over a substrate. A first conductive wire is formed over the first dielectric layer. A spacer structure is formed over the first conductive wire. The spacer structure is disposed along sidewalls of the first conductive wire. A second dielectric layer is deposited over and around the first conductive wire. The spacer structure is spaced between the first conductive wire and the second dielectric layer. A removal process is performed on the spacer structure and the second dielectric layer. An upper surface of the spacer structure is disposed above an upper surface of the first conductive wire.

公开(公告)号：US20210111029A1

公开(公告)日：2021-04-15

申请号：US17107484

申请日：2020-11-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih Wei Lu ,  Chung-Ju Lee ,  Hai-Ching Chen ,  Chien-Hua Huang ,  Tien-I Bao

IPC分类号： H01L21/28 ,  H01L21/768 ,  H01L29/49 ,  H01L23/485

摘要： A method of forming a semiconductor device includes providing a precursor. The precursor includes a substrate; a gate stack over the substrate; a first dielectric layer over the gate stack; a gate spacer on sidewalls of the gate stack and on sidewalls of the first dielectric layer; and source and drain (S/D) contacts on opposing sides of the gate stack. The method further includes recessing the gate spacer to at least partially expose the sidewalls of the first dielectric layer but not to expose the sidewalls of the gate stack. The method further includes forming a spacer protection layer over the gate spacer, the first dielectric layer, and the S/D contacts.

公开(公告)号：US10854458B2

公开(公告)日：2020-12-01

申请号：US16118744

申请日：2018-08-31

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih Wei Lu ,  Chung-Ju Lee ,  Hai-Ching Chen ,  Chien-Hua Huang ,  Tien-I Bao

IPC分类号： H01L21/28 ,  H01L21/768 ,  H01L29/49 ,  H01L23/485 ,  H01L29/78

摘要： A method of forming a semiconductor device includes providing a precursor. The precursor includes a substrate; a gate stack over the substrate; a first dielectric layer over the gate stack; a gate spacer on sidewalls of the gate stack and on sidewalls of the first dielectric layer; and source and drain (S/D) contacts on opposing sides of the gate stack. The method further includes recessing the gate spacer to at least partially expose the sidewalls of the first dielectric layer but not to expose the sidewalls of the gate stack. The method further includes forming a spacer protection layer over the gate spacer, the first dielectric layer, and the S/D contacts.

公开(公告)号：US20200152476A1

公开(公告)日：2020-05-14

申请号：US16717461

申请日：2019-12-17

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih-Ming Chang ,  Chih-Ming Lai ,  Ru-Gun Liu ,  Tsai-Sheng Gau ,  Chung-Ju Lee ,  Tien-I Bao ,  Shau-Lin Shue

IPC分类号： H01L21/321 ,  H01L23/522 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/768

摘要： An integrated circuit structure includes a first metal feature formed into a first dielectric layer, a second metal feature formed into a second dielectric layer, the second dielectric layer being disposed on said first dielectric layer, and a via connecting the first metal feature to the second metal feature, wherein a top portion of the via is offset from a bottom portion of the via.

公开(公告)号：US20200044044A1

公开(公告)日：2020-02-06

申请号：US16598087

申请日：2019-10-10

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Sheng Chang ,  Chung-Ju Lee ,  Tien-I Bao

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L21/8234 ,  H01L21/308 ,  H01L21/311 ,  H01L21/033 ,  H01L29/49

摘要： A method includes forming a spacer layer on a top surface and sidewalls of a patterned feature, wherein the patterned feature is overlying a base layer. A protection layer is formed to contact a top surface and a sidewall surface of the spacer layer. The horizontal portions of the protection layer are removed, wherein vertical portions of the protect layer remain after the removal. The spacer layer is etched to remove horizontal portions of the spacer layer, wherein vertical portions of the spacer layer remain to form parts of spacers.

公开(公告)号：US20190252204A1

公开(公告)日：2019-08-15

申请号：US16396463

申请日：2019-04-26

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Tsung-Min Huang ,  Chung-Ju Lee ,  Yung-Hsu Wu

IPC分类号： H01L21/311 ,  H01L21/027 ,  H01L21/02 ,  H01L21/768 ,  H01L21/033 ,  H01L21/308

CPC分类号： H01L21/31144 ,  H01L21/02118 ,  H01L21/0273 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31116 ,  H01L21/76816 ,  H01L21/76877

摘要： A method of patterning a semiconductor device is disclosed. A tri-layer photoresist is formed over a plurality of patterned features. The tri-layer photoresist includes a bottom layer, a middle layer disposed over the bottom layer, and a top layer disposed over the middle layer, the top layer containing a photo-sensitive material. The top layer is patterned via a photolithography process, the patterned top layer including an opening. The opening is extended into the bottom layer by etching the bottom layer and continuously forming a protective layer on etched surfaces of the bottom layer and on exposed surfaces of the patterned features. The bottom layer is removed. At least some portions of the protective layer remain on the exposed surfaces of the patterned features after the bottom layer is removed.

公开(公告)号：US20190122895A1

公开(公告)日：2019-04-25

申请号：US16229339

申请日：2018-12-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yung-Sung Yen ,  Chung-Ju Lee ,  Chun-Kuang Chen ,  Chia-Tien Wu ,  Ta-Ching Yu ,  Kuei-Shun Chen ,  Ru-Gun Liu ,  Shau-Lin Shue ,  Tsai-Sheng Gau ,  Yung-Hsu Wu

IPC分类号： H01L21/311 ,  H01L21/3213 ,  H01L21/033 ,  H01L21/768

CPC分类号： H01L21/31144 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L21/76816 ,  H01L21/823481 ,  H01L21/823878

摘要： A method includes forming a material layer over a substrate, forming a first hard mask (HM) layer over the material layer, forming a first trench, along a first direction, in the first HM layer. The method also includes forming first spacers along sidewalls of the first trench, forming a second trench in the first HM layer parallel to the first trench, by using the first spacers to guard the first trench. The method also includes etching the material layer through the first trench and the second trench, removing the first HM layer and the first spacers, forming a second HM layer over the material layer, forming a third trench in the second HM layer. The third trench extends along a second direction that is perpendicular to the first direction and overlaps with the first trench. The method also includes etching the material layer through the third trench.

公开(公告)号：US20180374708A1

公开(公告)日：2018-12-27

申请号：US16118744

申请日：2018-08-31

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih Wei Lu ,  Chung-Ju Lee ,  Hai-Ching Chen ,  Chien-Hua Huang ,  Tien-I Bao

IPC分类号： H01L21/28 ,  H01L21/768 ,  H01L29/49 ,  H01L23/485 ,  H01L29/78

摘要： A method of forming a semiconductor device includes providing a precursor. The precursor includes a substrate; a gate stack over the substrate; a first dielectric layer over the gate stack; a gate spacer on sidewalls of the gate stack and on sidewalls of the first dielectric layer; and source and drain (S/D) contacts on opposing sides of the gate stack. The method further includes recessing the gate spacer to at least partially expose the sidewalls of the first dielectric layer but not to expose the sidewalls of the gate stack. The method further includes forming a spacer protection layer over the gate spacer, the first dielectric layer, and the S/D contacts.

公开(公告)号：US10163887B2

公开(公告)日：2018-12-25

申请号：US15952316

申请日：2018-04-13

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih Wei Lu ,  Chung-Ju Lee ,  Chien-Hua Huang ,  Hsiang-Ku Shen ,  Zhao-Cheng Chen

IPC分类号： H01L21/8234 ,  H01L27/02 ,  H01L27/088 ,  H01L21/768 ,  H01L21/3105 ,  H01L23/528 ,  H01L29/66 ,  H01L21/467 ,  H01L23/522 ,  H01L29/06

摘要： A semiconductor device includes a first gate stack over an insulator, a second gate stack over an active region, a first dielectric layer over the first and second gate stacks, a second dielectric layer over the first dielectric layer, and a metal layer over the first and second gate stacks. The first and second dielectric layers include different materials. The metal layer contacts the second gate stack by penetrating at least the first and second dielectric layers and is isolated from the first gate stack by at least the first and second dielectric layers.